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SN74ACT7813-25DLR データシート(PDF) 1 Page - Texas Instruments

部品番号 SN74ACT7813-25DLR
部品情報  64 x18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
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メーカー  TI [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI - Texas Instruments

SN74ACT7813-25DLR データシート(HTML) 1 Page - Texas Instruments

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SN74ACT7813
64
× 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS199B – JANUARY 1991 – REVISED APRIL 1998
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Member of the Texas Instruments
Widebus
™ Family
D Free-Running Read and Write Clocks Can
Be Asynchronous or Coincident
D Read and Write Operations Synchronized
to Independent System Clocks
D Input-Ready Flag Synchronized to Write
Clock
D Output-Ready Flag Synchronized to Read
Clock
D 64 Words by 18 Bits
D Low-Power Advanced CMOS Technology
D Half-Full Flag and Programmable
Almost-Full/Almost-Empty Flag
D Bidirectional Configuration and Width
Expansion Without Additional Logic
D Fast Access Times of 12 ns With a 50-pF
Load and All Data Outputs Switching
Simultaneously
D Data Rates up to 67 MHz
D Pin-to-Pin Compatible With SN74ACT7803
and SN74ACT7805
D Packaged in Shrink Small-Outline 300-mil
Package Using 25-mil Center-to-Center
Spacing
description
The SN74ACT7813 is a 64-word
× 18-bit FIFO
suited for buffering asynchronous datapaths up to
67-MHz clock rates and 12-ns access times. Two
devices can be configured for bidirectional data buffering without additional logic. Multiple distributed VCC and
GND pins, along with Texas Instruments patented output edge control (OEC
™) circuit, dampen simultaneous
switching noise.
The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident.
Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low, and input
ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and OE2 are low
and output ready (OR) is high. The first word written to memory is clocked through to the output buffer regardless
of the RDEN, OE1, and OE2 levels. The OR flag indicates that valid data is present on the output buffer.
The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET must be asserted while at least four
WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes
the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be
reset upon power up.
The SN74ACT7813 is characterized for operation from 0
°C to 70°C.
Copyright
© 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Widebus and OEC are trademarks of Texas Instruments Incorporated.
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RESET
D17
D16
D15
D14
D13
D12
D11
D10
VCC
D9
D8
GND
D7
D6
D5
D4
D3
D2
D1
D0
HF
PEN
AF/AE
WRTCLK
WRTEN2
WRTEN1
IR
OE1
Q17
Q16
Q15
GND
Q14
VCC
Q13
Q12
Q11
Q10
Q9
GND
Q8
Q7
Q6
Q5
VCC
Q4
Q3
Q2
GND
Q1
Q0
RDCLK
RDEN
OE2
OR
DL PACKAGE
(TOP VIEW)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.


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