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CAT28C64BGI-15T データシート(PDF) 11 Page - ON Semiconductor |
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CAT28C64BGI-15T データシート(HTML) 11 Page - ON Semiconductor |
11 / 13 page CAT28C64B 11 Doc. No. MD-1011, Rev. I © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice To activate the software data protection, the device must be sent three write commands to specific addresses with specific data (Figure 9). This sequence of commands (along with subsequent writes) must adhere to the page write timing specifications (Figure 11). Once this is done, all subsequent byte or page writes to the device must be preceded by this same set of write commands. The data protection mechanism is activated until a deactivate sequence is issued regardless of power on/off transitions. This gives the user added inadvertent write protection on power-up in addition to the hardware protection provided. To allow the user the ability to program the device with an EEPROM programmer (or for testing purposes) there is a software command sequence for deactivating the data protection. The six step algorithm (Figure 10) will reset the internal protection circuitry, and the device will return to standard operating mode (Figure 12 provides reset timing). After the sixth byte of this reset sequence has been issued, standard byte or page writing can commence. Figure 11. Software Data Protection Timing CE WE tWP AA 1555 55 0AAA A0 1555 DATA ADDRESS tBLC tWC BYTE OR PAGE WRITES ENABLED Figure 12. Resetting Software Data Protection Timing CE WE AA 1555 55 0AAA DATA ADDRESS tWC 80 1555 AA 1555 55 0AAA 20 1555 SDP RESET DEVICE UNPROTECTED Speed 90: 90ns 12: 120ns 15: 150ns |
同様の部品番号 - CAT28C64BGI-15T |
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同様の説明 - CAT28C64BGI-15T |
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