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74LVC07APW-T データシート(PDF) 7 Page - NXP Semiconductors |
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74LVC07APW-T データシート(HTML) 7 Page - NXP Semiconductors |
7 / 14 page 74LVC07A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 27 October 2011 7 of 14 NXP Semiconductors 74LVC07A Hex buffer with open-drain outputs Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 7. Load circuitry for measuring switching times VM VM tW tW 10 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % tf tr tr tf 001aae331 VEXT VCC VI VO DUT CL RT RL RL G Table 9. Test data Supply voltage Input Load VEXT VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 1.2 V VCC 2 ns 30 pF 1 k open 2 V CC GND 1.65 V to 1.95 V VCC 2 ns 30 pF 1 k open 2 V CC GND 2.3 V to 2.7 V VCC 2 ns 30 pF 500 open 2 V CC GND 2.7V 2.7V 2.5 ns 50 pF 500 open 2 V CC GND 3.0Vto 3.6V 2.7V 2.5 ns 50 pF 500 open 2 V CC GND 4.5 V to 5.5 V VCC 2.5 ns 50 pF 500 open 2 V CC GND |
同様の部品番号 - 74LVC07APW-T |
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同様の説明 - 74LVC07APW-T |
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