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SL18860DC データシート(PDF) 4 Page - Silicon Laboratories |
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SL18860DC データシート(HTML) 4 Page - Silicon Laboratories |
4 / 12 page Rev 1.8, March 16 , 2012 Page 4 of 12 SL18860DC AC Electrical Characteristics (I-Grade) Unless otherwise stated VDD= 1.8V+/- 5% and Operation Temperature Range -40 to +85°C Parameter Symbol Condition Min Typ Max Unit Input Clock Range CLKIN External Clock, CMOS square wave 10 26.000 52 MHz Output Clock Range CLKOUT External Clock, CMOS square wave CLKOUT1/2/3 10 26.000 52 MHz Input Clock Voltage Swing Level VINpp VDD=1.8V 0.72 1 - Vpp Input Duty Cycle DCIN CLKIN, Pin 3 30 50 70 % Output Clock Rise Time tr VDD=1.8, CL=10pF, measured from 10 to 90% of VDD, Pins 4, 8, 9 and 10 - 2.0 4.00 ns Output Clock Fall Time tf VDD=1.8, CL=10pF, measured from 10 to 90% of VDD, Pins 4, 8, 9 and 10 - 2.0 4.00 ns Additive Phase Noise APN-1 CLKIN=26MHz and 1 kHz offset CLKOUT1/2/3 - -140 - dBc/Hz Additive Phase Noise APN-2 CLKIN=26MHz and 10 kHz offset CLKOUT1/2/3 - -150 - dBc/Hz Additive Phase Noise APN-3 CLKIN=26MHz and 100 kHz offset CLKOUT1/2/3 - -159 - dBc/Hz Power-up Time tPU Time duration until CLKOUT1/2/3 frequency reaches valid frequency after power supply reaches 0.9xVDD value - 100 200 Ns Output Enable Time tOE1 Time from OE raising edge to active at outputs CLKOUT1/2/3 (Asynchronous) - 25 - ns Output Disable Time tOD Time from OE falling edge to Hi-Z at outputs CLKOUT1/2/3 (Asynchronous) - 25 - ns Output Enable Time tOE2 Active recovery time from standby (CLKIN=0 or 1) to active at outputs CLKOUT1/2/3 - 100 - Ns |
同様の部品番号 - SL18860DC |
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同様の説明 - SL18860DC |
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