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AD7569SE2 データシート(PDF) 4 Page - Analog Devices |
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AD7569SE2 データシート(HTML) 4 Page - Analog Devices |
4 / 20 page AD7569/AD7669–TIMING CHARACTERISTICS1 Limit at Limit at Limit at TMIN, TMAX TMIN, TMAX Parameter 25 C (All Grades) (J, K, A, B Grades) (S, T Grades) Units Test Conditions/Comments DAC Timing t1 80 80 90 ns min WR Pulse Width t2 0 0 0 ns min CS , A/B to WR Setup Time t3 0 0 0 ns min CS , A/B to WR Hold Time t4 60 70 80 ns min Data Valid to WR Setup Time t5 10 10 10 ns min Data Valid to WR Hold Time ADC Timing t6 50 50 50 ns min ST Pulse Width t7 110 130 150 ns max ST to BUSY Delay t8 20 30 30 ns max BUSY to INT Delay t9 0 0 0 ns min BUSY to CS Delay t10 0 0 0 ns min CS to RD Setup Time t11 60 75 90 ns min RD Pulse Width Determined by t13. t12 0 0 0 ns min CS to RD Hold Time t13 2 60 75 90 ns max Data Access Time after RD; CL = 20 pF 95 120 135 ns max Data Access Time after RD; CL = 100 pF t14 3 10 10 10 ns min Bus Relinquish Time after RD 60 75 85 ns max t15 65 75 85 ns max RD to INT Delay t16 120 140 160 ns max RD to BUSY Delay t17 2 60 75 90 ns max Data Valid Time after BUSY; CL = 20 pF 90 115 135 ns max Data Valid Time after BUSY; CL = 100 pF NOTES 1Sample tested at +25 °C to ensure compliance. All input control signals are specified with t R = tF = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. 2t 13 and t17 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross either 0.8 V or 2.4 V. 3t l4 is defined as the time required for the data line to change 0.5 V when loaded with the circuit of Figure 2. Specifications subject to change without notice. REV. B –4– WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7569/AD7669 features proprietary ESD protection circuitry, permanent dam- age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ABSOLUTE MAXIMUM RATINGS VDD to AGNDDAC or AGNDADC . . . . . . . . . . . . . –0.3 V, +7 V VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +14 V AGNDDAC or AGNDADC to DGND . . . . –0.3 V, VDD + 0.3 V AGNDDAC to AGNDADC . . . . . . . . . . . . . . . . . . . . . . . . . ±5 V Logic Voltage to DGND . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V CLK Input Voltage to DGND . . . . . . . . . –0.3 V, VDD + 0.3 V VOUT (VOUTA, VOUTB) to AGND 1 DAC . . . . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V VIN to AGNDADC . . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V NOTE 1Output may be shorted to any voltage in the range V SS to VDD provided that the power dissipation of the package is not exceeded. Typical short circuit current for a short to AGND or VSS is 50 mA. Figure 1. Load Circuits for Data Access Time Test a. High-Z to VOH Figure 2. Load Circuits for Bus Relinquish Time Test b. High-Z to VOL a. VOH to High-Z b. VOL to High-Z Power Dissipation (Any Package) to +75 °C . . . . . . . . 450 mW Derates above 75 °C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C Operating Temperature Range Commercial (J, K) . . . . . . . . . . . . . . . . . . . . . . 0 °C to +70°C Industrial (A, B) . . . . . . . . . . . . . . . . . . . . . –40 °C to +85°C Extended (S, T) . . . . . . . . . . . . . . . . . . . . –55 °C to +125°C Storage Temperature Range . . . . . . . . . . . . –65 °C to +150°C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300 °C *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. (See Figures 8, 10, 12; VDD = 5 V 5%; VSS = 0 V or –5 V 5%) |
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同様の説明 - AD7569SE2 |
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