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AD5392BSTZ-3 データシート(PDF) 8 Page - Analog Devices |
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AD5392BSTZ-3 データシート(HTML) 8 Page - Analog Devices |
8 / 40 page AD5381 Data Sheet Rev. D | Page 8 of 40 TIMING CHARACTERISTICS SERIAL INTERFACE TIMING DVDD = 2.7 V to 5.5 V; AVDD= 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications T MIN to TMAX, unless otherwise noted. Table 5. Parameter 1, 2, 3 Limit at T MIN, TMAX Unit Description t 1 33 ns min SCLK cycle time t 2 13 ns min SCLK high time t 3 13 ns min SCLK low time t 4 13 ns min SYNC falling edge to SCLK falling edge setup time t 5 4 13 ns min 24th SCLK falling edge to SYNC falling edge t 6 4 33 ns min Minimum SYNC low time t 7 10 ns min Minimum SYNC high time t 7A 50 ns min Minimum SYNC high time in Readback mode t 8 5 ns min Data setup time t 9 4.5 ns min Data hold time t 10 4 30 ns max 24th SCLK falling edge to BUSY falling edge t 11 670 ns max BUSY pulse width low (single channel update) t 12 4 20 ns min 24th SCLK falling edge to LDAC falling edge t 13 20 ns min LDAC pulse width low t 14 2 µs max BUSY rising edge to DAC output response time t 15 0 ns min BUSY rising edge to LDAC falling edge t 16 100 ns min LDAC falling edge to DAC output response time t 17 3 µs typ DAC output settling time t 18 20 ns min CLR pulse width low t 19 40 µs max CLR pulse activation time t 20 5 20 ns max SCLK rising edge to SDO valid t 21 5 5 ns min SCLK falling edge to SYNC rising edge t 22 5 8 ns min SYNC rising edge to SCLK rising edge t 23 20 ns min SYNC rising edge to LDAC falling edge 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with t r = tf = 5 ns (10% to 90% of VCC) and are timed from a voltage level of 1.2 V. 3 See Figure 2, Figure 3, Figure 4, and Figure 5. 4 Standalone mode only. 5 Daisy-chain mode only. CL 50pF TO OUTPUT PIN VOH (MIN) OR VOL (MAX) 200 µA 200 µA IOL IOH Figure 2. Load Circuit for Digital Output Timing |
同様の部品番号 - AD5392BSTZ-3 |
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同様の説明 - AD5392BSTZ-3 |
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