CDCVF25084

3.3-V 1:8 ZERO DELAY (PLL) x4 CLOCK MULTIPLIER

SCAS690A – APRIL 2003 – REVISED MAY 2003

6

POST OFFICE BOX 655303

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

t(lock)

PLL lock time

fout = 100 MHz

2

µs

t

Phase offset (CLKIN to FBIN), (see

fout = 40 MHz to 75 MHz, Vth = VDD/2

±200

ps

t(phoffset)

Phase offset (CLKIN to FBIN), (see

Note 5)

fout = 75 MHz to 180 MHz, Vth = VDD/2

±100

ps

tPLH, tPHL Propagation delay

S2 = High, S1 = Low (PLL bypass mode)

2.3

4.5

ns

tsk(o)

Output skew (Yn to Yn) (see Note 4)

See Figure 3

75

150

ps

Pt t

t k

PLL bypass mode

900

tsk(pp)

Part-to-part skew

(low-to-high transition)

PLL mode, fout = 40 MHz to 75 MHz

350

ps

tsk( )

(low-to-high transition)

PLL mode, fout = 75 MHz to 180 MHz

300

s

t

Jitter (cycle to cycle)

fout = 40 MHz to 75 MHz

±220

ps

tjit(cc)

Jitter (cycle-to-cycle)

fout = 75 MHz to 180 MHz

±120

ps

t

Period jitter

fout = 40 MHz to 75 MHz

260

ps

tjit(per)

Period jitter

fout = 75 MHz to 180 MHz

140

ps

tjit(

θ)

Phase jitter

fout = 75 MHz to 180 MHz, peak-to-peak

(see Note 6)

±110

ps

tjit(

θ)

Phase jitter

fout = 75 MHz to 180 MHz, RMS (see Note 6)

26

ps

odc

Output duty cycle

fout = 10 MHz to 180 MHz

45%

55%

tsk(p)

Pulse skew

S2 = High, S1 = low (PLL bypass mode)

0.3

ns

tr, tf

Rise / fall time rate

See Figure 4

1

3

V/ns

† All typical values are at respective nominal VDD.

NOTES:

4. The tsk(o) specification is only valid for equal loading of all outputs.

5. Similar waveform at CLKIN and FBIN are required. Output 1Y3 is used as a feedback to FBIN loaded with 11 pF and all other outputs

have 15 pF. For phase displacement between CLKIN and Y-outputs, see Figure 5.

6. Input phase jitter

<±50 ps; output sample size is 20000 cycles.