SN74ACT7882

2048

× 18

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS445C – JUNE 1994 – REVISED APRIL 1998

5

POST OFFICE BOX 655303

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

AF/AE

33

O

Almost-full/almost-empty flag. The AF/AE boundary is defined by the AF/AE offset value (X). This

value can be programmed during reset or the default value of 256 can be used. AF/AE is high when

the number of words in memory is less than or equal to X. AF/AE also is high when the number of words

in memory is greater than or equal to (2048 – X).

Programming the AF/AE offset value (X) is accomplished during a reset cycle. The AF/AE offset value

(X) is either user-defined or the default value of X = 256. The procedure to program AF/AE is as follows:

User-defined X

Step 1: Take DAF from high to low. The high-to-low transition of DAF input stores the binary value

on the data inputs as X. The following bits are used, listed from most significant bit to least significant

bit D9–D0.

Step 2: If RESET is not already low, take RESET low.

Step 3: With DAF held low, take RESET high. This defines the AF/AE using X.

NOTE: To retain the current (X) offset, keep DAF low during subsequent reset cycles.

Default X

To redefine AF/AE using the default value of X = 256, hold DAF high during the reset cycle.

DAF

27

I

Define almost-full. The high-to-low transition of DAF stores the binary value of data inputs as the AF/AE

offset value (X). With DAF held low, a RESET cycle defines the AF/AE flag using X.

D0–D17

26–19, 17,

15–7

I

Data inputs for 18-bit-wide data to be stored in the memory. A high-to-low transition on DAF captures

data for the almost-empty/almost-full offset (X) from D9–D0.

HF

36

O

Half-full flag. HF is high when the FIFO contains 1024 or more words and is low when the number of

words in memory is less than half the depth of the FIFO.

IR

35

O

Input-ready flag. IR is high when the FIFO is not full and low when the device is full. During reset, IR

is driven low on the rising edge of the second WRTCLK pulse. IR then is driven high on the rising edge

of the second WRTCLK pulse after RESET goes high. After the FIFO is filled and IR is driven low, IR

is driven high on the second WRTCLK pulse after the first valid read.

OE

2

I

Output enable. The Q0–Q17 outputs are in the high-impedance state when OE is low. OE must be high

before the rising edge of RDCLK to read a word from memory.

OR

66

O

Output-ready flag. OR is high when the FIFO is not empty and low when it is empty. During reset, OR

is set low on the rising edge of the third RDCLK pulse. OR is set high on the rising edge of the third

RDCLK pulse to occur after the first word is written into the FIFO. OR is set low on the rising edge of

the first RDCLK pulse after the last word is read.

Q0–Q17

38–39, 41–42,

44, 46–47,

49–50, 52–53,

55–56, 58–59,

61, 63–64

O

Data out. The first data word to be loaded into the FIFO is moved to Q0–Q17 on the rising edge of the

third RDCLK pulse to occur after the first valid write. RDEN1 and RDEN2 do not affect this operation.

Following data is unloaded on the rising edge of RDCLK when RDEN1, RDEN2, OE, and OR are high.

RDCLK

5

I

Read clock. Data is read out of memory on the low-to-high transition at RDCLK if OR, OE, and RDEN1

and RDEN2 are high. RDCLK is a free-running clock and functions as the synchronizing clock for all

data transfers out of the FIFO. OR also is driven synchronously with respect to RDCLK.

RDEN1

RDEN2

4

3

I

Read enable. RDEN1 and RDEN2 must be high before a rising edge on RDCLK to read a word out

of memory. RDEN1 and RDEN2 are not used to read the first word stored in memory.

RESET

1

I

Reset. A reset is accomplished by taking RESET low and generating a minimum of four RDCLK and

WRTCLK cycles. This ensures that the internal read and write pointers are reset and that OR, HF, and

IR are low, and AF/AE is high. The FIFO must be reset upon power up. With DAF at a low level, a low

pulse on RESET defines AF/AE using the AF/AE offset value (X), where X is the value previously

stored. DAF held high during a RESET cycle defines the AF/AE flag using the default value of X = 256.

WRTCLK

29

I

Write clock. Data is written into memory on a low-to-high transition of WRTCLK if IR, WRTEN1, and

WRTEN2 are high. WRTCLK is a free-running clock and functions as the synchronizing clock for all

data transfers into the FIFO. IR also is driven synchronously with respect to WRTCLK.

WRTEN1

WRTEN2

30

31

I

Write enable. WRTEN1 and WRTEN2 must be high before a rising edge on WRTCLK for a word to

be written into memory. WRTEN1 and WRTEN2 do not affect the storage of the AF/AE offset value (X).

† Terminals listed are for the FN package.