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TPIC46L01DBLE データシート(PDF) 9 Page - Texas Instruments |
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TPIC46L01DBLE データシート(HTML) 9 Page - Texas Instruments |
9 / 23 page TPIC46L01, TPIC46L02, TPIC46L03 6CHANNEL SERIAL AND PARALLEL LOW SIDE PREFET DRIVER SLIS055B − NOVEMBER 1996 − REVISED AUGUST 2001 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION serial data operation The TPIC46L01, TPIC46L02, and TPIC46L03 offer serial input interfaces to the microcontroller to transfer control data to the predriver and output fault data back to the controller. The serial input interface consists of: D SCLK − Serial clock D CS − Chip select D SDI − Serial data input D SDO − Serial data outpu Serial data is shifted into the least significant bit (LSB) of the SDI shift register on the rising edge of the first SCLK after CS has transitioned from 1 to 0. Eight clock cycles are required to shift the first bit from the LSB to the most significant bit (MSB) of the shift register. Less than eight clock cycles result in fault data being latched into the output control buffer. The first two bits are unused and the last six bits are the output control data. A low-to-high transition on CS latches the contents of the serial shift register into the output control register. A 0 input to SDI turns the corresponding parallel output off and a 1 turns the output on (see Figure 12). Don’t Care 12 3 4 5 6 7 8 GATE5 OFF GATE4 ON GATE3 ON GATE2 OFF GATE1 OFF GATE0 ON Present Output Data New Data SCLK CS SDI New Data Output Control Register Data Figure 12 |
同様の部品番号 - TPIC46L01DBLE |
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