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CAT28C256LI15 データシート(PDF) 5 Page - ON Semiconductor |
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CAT28C256LI15 データシート(HTML) 5 Page - ON Semiconductor |
5 / 14 page CAT28C256 http://onsemi.com 5 Table 7. A.C. CHARACTERISTICS, WRITE CYCLE (VCC = 5 V ±10%, unless otherwise specified.) Symbol Parameter 28C256−12 28C256−15 Units Min Max Min Max tWC Write Cycle Time 5 5 ms tAS Address Setup Time 0 0 ns tAH Address Hold Time 50 50 ns tCS CE Setup Time 0 0 ns tCH CE Hold Time 0 0 ns tCW (Note 10) CE Pulse Time 100 100 ns tOES OE Setup Time 0 0 ns tOEH OE Hold Time 0 0 ns tWP (Note 10) WE Pulse Width 100 100 ns tDS Data Setup Time 50 50 ns tDH Data Hold Time 10 10 ns tINIT (Note 11) Write Inhibit Period After Power−up 5 10 5 10 ms tBLC (Notes 11, 12) Byte Load Cycle Time 0.1 100 0.1 100 ms 10.A write pulse of less than 20 ns duration will not initiate a write cycle. 11. This parameter is tested initially and after a design or process change that affects the parameter. 12.A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin; however a transition from HIGH to LOW within tBLC max. stops the timer. Figure 2. A.C. Testing Input/Output Waveform (Note 13) INPUT PULSE LEVELS REFERENCE POINTS 2.0 V 0.8 V 0.0 V VCC − 0.3 V 13.Input rise and fall times (10% and 90%) < 10 ns. Figure 3. A.C. Testing Load Circuit (example) 1.3 V DEVICE UNDER TEST 1N914 3.3 K OUT CL = 100 pF CL INCLUDES JIG CAPACITANCE |
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同様の説明 - CAT28C256LI15 |
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