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AD9249BBCZRL7-65 データシート(PDF) 7 Page - Analog Devices |
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AD9249BBCZRL7-65 データシート(HTML) 7 Page - Analog Devices |
7 / 36 page Data Sheet AD9249 Rev. 0 | Page 7 of 36 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted. Table 4. Parameter1, 2 Symbol Temp Min Typ Max Unit CLOCK3 Input Clock Rate Full 10 520 MHz Conversion Rate Full 10 65 MSPS Clock Pulse Width High tEH Full 7.69 ns Clock Pulse Width Low tEL Full 7.69 ns OUTPUT PARAMETERS3 Propagation Delay tPD Full 1.5 2.3 3.1 ns Rise Time (20% to 80%) tR Full 300 ps Fall Time (20% to 80%) tF Full 300 ps FCO±1, FCO±2 Propagation Delay tFCO Full 1.5 2.3 3.1 ns DCO±1, DCO±2 Propagation Delay4 tCPD Full tFCO + (tSAMPLE/28) ns DCO±1, DCO±2 to Data Delay4 tDATA Full (tSAMPLE/28) − 300 (tSAMPLE/28) (tSAMPLE/28) + 300 ps DCO±1, DCO±2 to FCO±1, FCO±2 Delay4 tFRAME Full (tSAMPLE/28) − 300 (tSAMPLE/28) (tSAMPLE/28) + 300 ps Data to Data Skew tDATA-MAX − tDATA-MIN Full ±50 ±200 ps Wake-Up Time (Standby) 25°C 35 μs Wake-Up Time (Power-Down)5 25°C 375 μs Pipeline Latency Full 16 Clock cycles APERTURE Aperture Delay tA 25°C 1 ns Aperture Uncertainty (Jitter) tJ 25°C 135 fs rms Out-of-Range Recovery Time 25°C 1 Clock cycles 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Measured on standard FR-4 material. 3 Adjustable using the SPI. 4 tSAMPLE/28 is based on the number of bits, divided by 2, because the delays are based on half duty cycles. tSAMPLE = 1/fSAMPLE. 5 Wake-up time is defined as the time required to return to normal operation from power-down mode. |
同様の部品番号 - AD9249BBCZRL7-65 |
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同様の説明 - AD9249BBCZRL7-65 |
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