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54F175DMQB データシート(PDF) 5 Page - Texas Instruments

部品番号 54F175DMQB
部品情報  LMP91050 Configurable AFE for Nondispersive Infrared (NDIR) Sensing Applications
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ホームページ  http://www.ti.com
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54F175DMQB データシート(HTML) 5 Page - Texas Instruments

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LMP91050
www.ti.com
SNAS517D – NOVEMBER 2011 – REVISED MARCH 2013
Electrical Characteristics
(1) (continued)
The following specifications apply for VDD = 3.3V, VCM = 1.15V, Bold values for TA = -40°C to +85°C unless otherwise
specified. All other limits apply to TA = TJ = +25°C.
Symbol
Parameter
Conditions
Min (2)
Typ (3)
Max (2)
Units
Programmable Gain Amplifier (PGA) 2nd Stage, RS = 1kΩ, CL = 1µF
VINMAX
Max input signal
GAIN = 4 V/V
1.65
V
VINMIN
Min input signal
0.82
V
G
Gain
Programmable in 4 steps
4
32
V/V
GE
Gain Error
Any gain
2.5
%
VDD –
VOUT
Output Voltage Range
0.2
V
0.2
100mV input sine 35kHz signal, Gain = 8, VOUT
PhDly
Phase Delay
1
µs
measured at 1.65V, RL = 10kΩ
Phase Delay variation with
250mV input step signal, Gain = 8, Vout
TCPhDly
84
ns
Temperature
measured at Vdd/2
SSBW
Small Signal Bandwidth
Gain = 32 V/V
360
kHz
Cin
Input Capacitance
5
pF
CLOAD,
OUT Pin Load Capacitance
Series RC
1
µF
OUT
RLOAD,
OUT Pin Load Resistance
Series RC
1
k
OUT
Combined Amplifier Chain Specification
Combination of both current and voltage noise,
en
Input-Referred Noise Density
with a 86k
Ω source impedance at 5Hz, Gain =
30
nV/
√Hz
7986
Combination of both current and voltage noise,
0.12
Input-Referred Integrated Noise with a 86k
Ω source impedance 0.1Hz to 10Hz,
0.1
µVrms
(4)
Gain = 7986
PGA1 GAIN = 42, PGA2 GAIN = 4
167
PGA1 GAIN = 42, PGA2 GAIN = 8
335
PGA1 GAIN = 42, PGA2 GAIN = 16
669
PGA1 GAIN = 42, PGA2 GAIN = 32
1335
G
Gain
V/V
PGA1 GAIN = 250, PGA2 GAIN = 4
1002
PGA1 GAIN = 250, PGA2 GAIN = 8
2004
PGA1 GAIN = 250, PGA2 GAIN = 16
4003
PGA1 GAIN = 250, PGA2 GAIN = 32
7986
GE
Gain Error
Any gain
5
%
TCCGE
Gain Temp Coefficient (5)
100
ppm/°C
PSRR
Power Supply Rejection Ratio
DC, 3.0V to 3.6V supply, gain = 1002V/V
90
110
dB
1mV input step signal, Gain = 1002, Vout
PhDly
Phase Delay
measured at Vdd/2
9
µs
Phase Delay variation with
1mV input step signal, Gain=1002, Vout
TCPhDly
Temperature (6)
measured at Vdd/2
500
ns
(4)
Specified by design and characterization. Not tested on shipped production material.
(5)
TCCGE and TCVOS are calculated by taking the largest slope between -40°C and 25°C linear interpolation and 25°C and 85°C linear
interpolation.
(6)
TCPhDly is largest change in phase delay between -40°C and 25°C measurements and 25°C and 85°C measurements.
Copyright © 2011–2013, Texas Instruments Incorporated
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