A[18:0]

GZ

DQ(31:0)

MBE

tGLMV

t

, t

AVQV1

AVMV

Data valid

Data valid

Assumptions: E1Z low, E2 high, WZ high and SCRUBZ high. Reading uninitialized addresses

will cause MBE to be asserted.

SMV512K32-SP

www.ti.com

SLVSA21H – JUNE 2011 – REVISED JULY 2013

Figure 6. Read Cycle 3, Output Enable-Controlled Access

Write Operation With Write-Through Support

A combination of WZ and E1Z low with E2 high defines a write cycle. The state of GZ is “don’t care” for a write

cycle although it may be necessary to set GZ high for convenient setup of new data for some system operation

modes in order to avoid data bus contention. During a write operation, data just written will be sent to the

outputs. When the write operation has been completed, the output data bus will be updated by controlling either

GZ going low or WZ goes high while GZ low. The outputs are placed in a high impedance state when GZ is high

or WZ is low during standard read and write cycles.

•

Write cycle 1 (Figure 7): Access and data write through controlled by WZ is initiated when WZ goes low and

•

Write cycle 1a (Figure 8): WZ controlled write cycle with GZ high is similar to write cycle 1 but with GZ fixed

high so data outputs remain in high impedance state.

•

Write cycle 2 (Figure 9): WZ controlled write access with data write through controlled by GZ is similar to

write cycle 1 with the difference being that the output data comes out when GZ goes low with WZ high. The

impedance state during the write operation to avoid bus contention.

•

Write cycle 3 (Figure 10): Chip enable controlled write access with data write through controlled by WZ is

initiated when E1Z or E2 goes active, and the data write operation is terminated by WZ going high. The write

•

Write cycle 3a (Figure 11): chip enabled controlled write cycle with GZ high is similar to write cycle3, but with

GZ fixed high so the data outputs remain in a high impedance state.

•

Write cycle 4 (Figure 12): Chip enable controlled write access with data write through controlled by GZ is

similar to Write cycle 3 with the difference that the data output is controlled by GZ going low. The output

impedance state during the write operation to avoid bus contention.

Copyright © 2011–2013, Texas Instruments Incorporated

Submit Documentation Feedback

9

Product Folder Links: SMV512K32-SP