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SMV512K32HFG データシート(PDF) 9 Page - Texas Instruments |
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SMV512K32HFG データシート(HTML) 9 Page - Texas Instruments |
9 / 25 page A[18:0] GZ DQ(31:0) MBE tGLQV tGLMV tGHQZ1 t , t AVQV1 AVMV tGLQX1 tGLMX tGHMZ Data valid Data valid Assumptions: E1Z low, E2 high, WZ high and SCRUBZ high. Reading uninitialized addresses will cause MBE to be asserted. tGHMZ SMV512K32-SP www.ti.com SLVSA21H – JUNE 2011 – REVISED JULY 2013 Figure 6. Read Cycle 3, Output Enable-Controlled Access Write Operation With Write-Through Support A combination of WZ and E1Z low with E2 high defines a write cycle. The state of GZ is “don’t care” for a write cycle although it may be necessary to set GZ high for convenient setup of new data for some system operation modes in order to avoid data bus contention. During a write operation, data just written will be sent to the outputs. When the write operation has been completed, the output data bus will be updated by controlling either GZ going low or WZ goes high while GZ low. The outputs are placed in a high impedance state when GZ is high or WZ is low during standard read and write cycles. • Write cycle 1 (Figure 7): Access and data write through controlled by WZ is initiated when WZ goes low and is terminated by WZ going high while E1Z and E2 remain active. The write pulse width is determined by tWLWH and tETWH. To avoid bus contention, tWLQZ must be satisfied before write data is applied to the DQ[31:0] pins. In addition, at the end of the write operation write data must be removed from the DQ[31:0] pins after tWHDX is met, but before tWHQX. The output access time is determined by tWHQV as long as GZ remains low. • Write cycle 1a (Figure 8): WZ controlled write cycle with GZ high is similar to write cycle 1 but with GZ fixed high so data outputs remain in high impedance state. • Write cycle 2 (Figure 9): WZ controlled write access with data write through controlled by GZ is similar to write cycle 1 with the difference being that the output data comes out when GZ goes low with WZ high. The output access time is determined by tGLQV. The GZ high pulse is used to keep the DQ[31:0] outputs in a high impedance state during the write operation to avoid bus contention. • Write cycle 3 (Figure 10): Chip enable controlled write access with data write through controlled by WZ is initiated when E1Z or E2 goes active, and the data write operation is terminated by WZ going high. The write pulse width is defined by tETWHZ from the latter of E1Z or E2 going active to WZ high. The output access time is determined by tWHQV as long as GZ remains low. As with write cycle 1, the write data must be removed from the DQ[31:0] pins after the input data hold time, tWHDX, but before tWHQX. • Write cycle 3a (Figure 11): chip enabled controlled write cycle with GZ high is similar to write cycle3, but with GZ fixed high so the data outputs remain in a high impedance state. • Write cycle 4 (Figure 12): Chip enable controlled write access with data write through controlled by GZ is similar to Write cycle 3 with the difference that the data output is controlled by GZ going low. The output access time is determined by tGLQV. The GZ high pulse is used to keep the DQ[31:0] pins in a high impedance state during the write operation to avoid bus contention. Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: SMV512K32-SP |
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