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AD7399BR-REEL データシート(PDF) 7 Page - Analog Devices |
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AD7399BR-REEL データシート(HTML) 7 Page - Analog Devices |
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7 / 24 page  AD7398/AD7399 Rev. C | Page 7 of 24 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 VOUTB 16 VOUTC 2 VOUTA 15 VOUTD 3 VSS 14 VDD 4 VREFA 13 VREFC 5 VREFB 12 VREFD 6 GND 11 SDI 7 LDAC 10 CLK 8 RS 9 CS AD7398/ AD7399 TOP VIEW (Not to Scale) Figure 5. Pin Configuration Table 4. Pin Function Descriptions Table 5. Control Logic Truth Table CS CLK LDAC Serial Shift Register Function Input Register Function DAC Register H X H No effect No effect No effect L L H No effect No effect No effect L ↑+ H Shift register data advanced one bit Latched No effect L H H No effect Latched No effect ↑+ L/H H No effect Updated with shift register contents No effect H X L No effect Latched Transparent H X ↑+ No effect Latched Latched NOTES 1. ↑+ = Positive logic transition; ↓– = Negative logic transition; X = Don’t Care. 2. At power-on, both the input register and the DAC register are loaded with all zeros. 3. During power shutdown, reprogramming of any internal registers can take place, but the output amplifiers do not produce the new values until the part is taken out of shutdown mode. 4. The LDAC input is a level-sensitive input that controls the four DAC registers. Pin No. Mnemonic Description 1 VOUTB DAC B Voltage Output. 2 VOUTA DAC A Voltage Output. 3 VSS Negative Power Supply Input. Specified range of operation 0 V to −5.5 V. 4 VREFA DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. Pin can be tied to VDD pin or VSS pin. 5 VREFB DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. Pin can be tied to VDD pin or VSS pin. 6 GND Ground Pin. 7 LDAC Load DAC Register Strobe. Level sensitive active low. Transfers all input register data to DAC registers. Asynchronous active low input. See Table 5 for operation. 8 RS Resets Input and DAC Registers to All Zero Codes. Shift register contents unchanged. 9 CS Chip Select. Active low input. Disables shift register loading when high. Transfers serial register data to the input register when CS returns high. Does not effect LDAC operation. 10 CLK Schmitt Triggered Clock Input. Positive edge clocks data into shift register. 11 SDI Serial Data Input. Input data loads directly into the shift register. 12 VREFD DAC D Reference Voltage Input Terminal. Establishes DAC D full-scale output voltage. Pin can be tied to VDD pin or VSS pin. 13 VREFC DAC C Reference Voltage Input Terminal. Establishes DAC C full-scale output voltage. Pin can be tied to VDD pin or VSS pin. 14 VDD Positive Power Supply Input. Specified range of operation 3 V to 5 V ± 10%. 15 VOUTD DAC D Voltage Output. 16 VOUTC DAC C Voltage Output. |
同様の部品番号 - AD7399BR-REEL |
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同様の説明 - AD7399BR-REEL |
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