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Motorola TMOS Power MOSFET Transistor Device Data

Designer's™ Data Sheet

Power Field Effect Transistor

D3PAK for Surface Mount

N–Channel Enhancement–Mode Silicon Gate

The D3PAK package has the capability of housing the largest chip

size of any standard, plastic, surface mount power semiconductor.

This allows it to be used in applications that require surface mount

components with higher power and lower RDS(on) capabilities. This

high voltage MOSFET uses an advanced termination scheme to

provide enhanced voltage–blocking capability without degrading

performance over time. In addition, this advanced TMOS E–FET is

designed to withstand high energy in the avalanche and commuta-

tion modes. The new energy efficient design also offers a drain–to–

source diode with a fast recovery time. Designed for high voltage,

high speed switching applications in surface mount PWM motor

controls and both ac–dc and dc–dc power supplies. These devices

are particularly well suited for bridge circuits where diode speed and

commutating safe operating areas are critical and offer additional

safety margin against unexpected voltage transients.

• Robust High Voltage Termination

• Avalanche Energy Specified

• Source–to–Drain Diode Recovery Time Comparable to a Discrete

Fast Recovery Diode

• Diode is Characterized for Use in Bridge Circuits

• IDSS and VDS(on) Specified at Elevated Temperature

• Short Heatsink Tab Manufactured – Not Sheared

• Specifically Designed Leadframe for Maximum Power Dissipation

• Available in 24 mm, 13–inch/500 Unit Tape & Reel, Add –RL Suffix to Part Number

Rating

Symbol

Value

Unit

Drain–to–Source Voltage

VDSS

1000

Vdc

Drain–to–Gate Voltage (RGS = 1.0 MΩ)

VDGR

1000

Vdc

Gate–to–Source Voltage — Continuous

VGS

VGSM

±20

±40

Vdc

Vpk

Drain Current — Continuous

°C

ID

ID

IDM

6.0

4.2

18

Adc

Apk

Total Power Dissipation

Derate above 25

°C

Total Power Dissipation @ TC = 25°C (1)

PD

178

1.43

2.0

Watts

W/

°C

Watts

Operating and Storage Temperature Range

TJ, Tstg

– 55 to 150

°C

Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C

(VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 6.0 Apk, L = 27.77 mH, RG = 25 Ω )

EAS

720

mJ

Thermal Resistance — Junction to Case

R

θJC

R

θJA

R

θJA

0.70

62.5

35

°C/W

Maximum Lead Temperature for Soldering Purposes, 1/8

″ from case for 10 seconds

TL

260

°C

(1) When surface mounted to an FR4 board using the minimum recommended pad size.

Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit

curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.

E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

Thermal Clad is a trademark of the Bergquist Company.

Order this document

by MTV6N100E/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

CASE 433–01, Style 2

D3PAK Surface Mount

MTV6N100E

TMOS POWER FET

6.0 AMPERES

1000 VOLTS

RDS(on) = 1.5 OHM

®

D

S

G

© Motorola, Inc. 1996