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AM79761YC-14 データシート(PDF) 7 Page - Advanced Micro Devices

部品番号 AM79761YC-14
部品情報  Physical Layer 10-Bit Transceiver for Gigabit Ethernet (GigaPHY??SD)
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メーカー  AMD [Advanced Micro Devices]
ホームページ  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM79761YC-14 データシート(HTML) 7 Page - Advanced Micro Devices

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Am79761
7
PRELIMINARY
PIN DESCRIPTION
TX+, TX-
Serial Transmit Data
PECL Output
These pins are the 1000BASE-X port differential driv-
ers which transmit the serial stream to the network.
These pins are connected to the copper or fiber optic
connectors.
When EWRAP is LOW, the pins assume normal oper-
ation. When HIGH, TX+ is logic HIGH and TX- is logic
LOW.
RX+, RX-
Serial Receive Data
PECL Input
These pins are the 1000BASE-X port differential re-
ceiver pair, receiving a serial stream of data from the
network. These pins are connected to the copper or
fiber optic connectors.
When EWRAP is LOW, the pins assume normal oper-
ation. The pins are internally biased.
TXD[0:9]
Transmit Data
TTL Input
The TXD[0:9] pin is a set of 10 data signals which are
driven from the Physical Coding Sublayer (PCS) above.
The 10 bits of data are clocked in parallel on the rising
edge of REFCLK. TXD0 is transmitted first on TX
±.
RXD[0:9]
Receive Data
TTL Output
The RXD[0:9] pin is a set of 10 data signals which are
sent to the Physical Coding Sublayer (PCS) above. The
10 bits of data are clocked out in parallel on the rising
edges of RCLK and RCLKN. RXD0 is received first on
RX
±.
REFCLK
Reference Clock
TTL Input
This input is used for the 125-Mhz clock. The rising
edge of this clock latches TXD[0:9] into an input regis-
ter. This clock serves as the reference clock at 1/10th
the baud rate for the PLL.
RCLK, RCLKN
Receive Clock
TTL Output
These pins provide the differential receive clock sig-
nals, derived from the RX
± data stream, and are at
1/20th the baud rate of the receive stream. Parallel data
on RXD[0:9] is provided at each rising transition of
RCLK and RCLKN.
EN_CDET
Enable Comma Detect
TTL Input
This pin is used to enable the word synchronization
mode. When logic HIGH, the COM_DET output is en-
abled and word synchronization is active.
COM_DET
Comma Detect Indicator
TTL Output
Comma Detect is asserted to indicate that the incoming
word on RXD[0:9] contains a Comma character
(0011111xxx). COM_DET goes HIGH for half of a RCLK
period, and can be captured when RCKLN is rising.
In order for COM_DET to provide indication, EN_CDET
must be enabled (logic HIGH).
EWRAP
Loopback Enable
TTL Input
When EWRAP is asserted, the transmitted data stream
is sent back to the receiver through an internal loop-
back path. TX+ is logic HIGH, and TX- is logic LOW in
this mode.
This pin is logic LOW for normal operation.
TEST[1:3]
Factory Test Pins
Input
These pins should be tied to DVDD for normal operation.
TEST[4]
Factory Test Pin
Output
This pin should be left unconnected for normal operation.
DVDD
Power
These pins supply power to the digital blocks of the
device. They must be connected to a 3.3 V
±5% source.
DVDD_T
TTL Power
These pins supply power to the TTL blocks of the de-
vice. They must be connected to a 3.3 V
±5% source.
DVDD_P
PECL Power
These pins supply power to the PECL blocks of the de-
vice. They must be connected to a 3.3 V
±5% source. It
is critical that the signal supplied to these pins are
clean to ensure good performance of the device.


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