AM79C100JC datasheet(5/24 Pages) AMD

部品番号	AM79C100JC

部品情報	Twisted-Pair Ethernet Transceiver Plus (TPEX Plus)

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メーカー	AMD [Advanced Micro Devices]

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Am79C100

5

PIN DESCRIPTION

AV

DD

Analog Power

This pin supplies +5 V to analog portions of the TPEX

Plus circuitry.

AV

SS

Analog Ground

This pin is the ground reference for analog portions of

TPEX Plus circuitry.

CI+, CI–

Control In

Output

AUI port differential driver.

COL

Collision

Output, Open Drain

This pin is driven LOW while the TPEX Plus is simulta-

neously receiving data on the AUI DO pins and the

twisted-pair RXD pins, indicating that a collision condi-

tion exists. It is also driven if TPEX Plus enters the jab-

ber condition due to excessive length of activity on the

DO pair. In this case TPEX Plus will wait for a period of

inactivity on DO for the “unjab” time of 250 to 750 ms,

before the 10 MHz pattern on the CI pair is removed

and COL returns inactive. COL will not be driven during

SQE Test activity on the AUI CI pair. In the LOW output

state, the pin is capable of sinking a maximum of 12 mA

and can be used to drive an LED. The COL output is

pulse stretched for 20 to 62 ms after the end of colli-

sion, to ensure LED visibility.

DI+, DI–

Data In

Output

AUI port differential driver.

DO+, DO–

Data Out

Input

AUI port differential receiver.

DV

DD

Digital Power

This pin supplies +5 V to digital portions of the TPEX

Plus circuitry, including all transmit drivers.

DV

SS

Digital Ground

Two pins provide the ground reference for digital por-

tions of TPEX Plus circuitry, including all transmit

drivers and the status indication LED drivers.

LNKST

Link Status

Input/Output, Open Drain

When this pin is tied LOW, the internal Link Test Re-

ceive function is disabled, and the Transmit and

Receive functions will remain active regardless of arriv-

ing idle link pulses and data. TPEX Plus continues to

generate idle link pulses irrespective of the status of

this pin.

As an output, this pin is driven LOW if the link is identi-

fied as functional. However, if the link is determined to

be nonfunctional due to missing idle link pulses or data

packets, then this pin is not driven (internally pulled

HIGH). In the LOW output state, the pin is capable of

sinking a maximum of 12 mA and can be used to drive

an LED.

In the absence of an external drive, the pin is internally

pulled HIGH when inactive.

LRT

Low Receive Threshold

Input, Active LOW

When this pin is tied LOW, the internal twisted-pair re-

ceive thresholds are reduced by 4.5 dB from their orig-

inal values (approximately 3/5 of the normal 10BASE-T

value). With LRT in the HIGH state, the unsquelch

threshold for the RXD

± circuit will be 300 mV to 520 mV

peak. With LRT in the LOW state, the unsquelch

threshold for the RXD

± circuit will be 180 mV to 312 mV

peak. In either case, the RXD

± circuit post unsquelch

threshold will be approximately one-half of the initial

unsquelch threshold.

PRDN/RST

Power Down/Reset

Input, Active LOW

Driving this input LOW resets the internal logic of TPEX

Plus and places the device in a special Power Down

mode. In the Power Down/Reset mode, all output driv-

ers are placed in their inactive state.

REXT

External Resistor

Input

An external precision resistor is connected between

this pin and AV

DD in order to provide a current refer-

ence for the internal voltage-controlled oscillator

(VCO).

RCV

Receive

Output, Open Drain

This pin is driven LOW while TPEX Plus is receiving

data on the twisted-pair RXD pins and is transferring

the received signal onto the AUI DI pair. The output is

LOW during collision simultaneously with the COL pin.

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