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AM79C981JC データシート(PDF) 1 Page - Advanced Micro Devices

部品番号 AM79C981JC
部品情報  Integrated Multiport Repeater Plus??(IMR??
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メーカー  AMD [Advanced Micro Devices]
ホームページ  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM79C981JC データシート(HTML) 1 Page - Advanced Micro Devices

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PRELIMINARY
This document contains information on a product under development at Advanced Micro Devices. The
information is intended to help you evaluate this product. AMD reserves the right to change or discontinue
work on this proposed product without notice.
Publication# 17306
Rev: B Amendment/0
Issue Date: January 1999
1-71
Am79C981
Integrated Multiport Repeater Plus™ (IMR+™)
DISTINCTIVE CHARACTERISTICS
s Enhanced version of AMD’s Am79C980
Integrated Multiport Repeater™ (IMR™) chip
with the following enhancements:
— Additional management port features
— Minimum mode provides support for an extra
four LED outputs per port for additional status in
non-intelligent repeater designs
— Pin/socket-compatible with the Am79C980
IMR chip
— Fully backward-compatible with existing IMR
device designs
s Interfaces directly with the Am79C987 HIMIB™
device to build a fully managed multiport
repeater
s CMOS device features high integration and low
power with a single +5 V supply
s Repeater functions comply with IEEE 802.3
Repeater Unit specifications
s Eight integral 10BASE-T transceivers utilize the
required predistortion transmission technique
s Attachment unit interface (AUI) port allows
connectivity with 10BASE-5 (Ethernet) and
10BASE-2 (Cheapernet) networks, as well as
10BASE-F and/or Fiber Optic Inter-Repeater
Link (FOIRL) segments
s On-board PLL, Manchester encoder/decoder,
and FIFO
s Expandable to increase number of repeater
ports
s All ports can be separately isolated (partitioned)
in response to excessive collision conditions or
fault conditions
s Network management and optional features are
accessible through a dedicated serial
management port
s Twisted-pair Link Test capability conforming to
the 10BASE-T standard. The receive Link Test
function can be optionally disabled through the
management port to facilitate interoperability
with devices that do not implement the Link Test
function
s Programmable option of Automatic Polarity
Detection and Correction permits automatic
recovery due to wiring errors
s Full amplitude and timing regeneration for
retransmitted waveforms
s Preamble loss effects eliminated by deep FIFO
GENERAL DESCRIPTION
The Integrated Multiport Repeater Plus (IMR+) chip is a
VLSI circuit that provides a system-level solution to de-
signing a compliant 802.3 repeater incorporating
10BASE-T transceivers. The device integrates the
Repeater functions specified by Section 9 of the IEEE
802.3 standard and Twisted-Pair Transceiver functions
complying with the 10BASE-T standard. The Am79C981
provides eight integral twisted-pair medium attachment
units (MAUs) and an attachment unit interface (AUI) port
in an 84-pin plastic leaded chip carrier (PLCC).
A network based on the 10BASE-T standard uses un-
shielded twisted-pair cables, thereby providing an eco-
nomical solution to networking by allowing the use of
low-cost unshielded twisted-pair (UTP) cable or existing
telephone wiring.
The total number of ports per repeater unit can be in-
creased by connecting multiple IMR+ devices through
their expansion ports, minimizing the total cost per re-
peater port. Furthermore, a general-purpose attach-
ment unit interface (AUI) provides connection capability
to 10BASE-5 (Ethernet) and 10BASE-2 (Cheapernet)
coaxial networks, as well as 10BASE-F and/or Fiber
Optic Inter-Repeater Link (FOIRL) fiber segments. Net-
work management and test functions are provided
through TTL-compatible I/O pins.
The IMR+ device interfaces directly with AMD’s
Am79C987 Hardware Implemented Management In-
formation Base™ (HIMIB) chip to build a fully managed
multiport repeater as specified by the IEEE 802.3
(Layer Management for 10 Mb/s Baseband Repeaters)
standard. When the IMR+ and HIMIB devices are
interconnected, complete repeater and per-port statis-
tics are maintained and can be accessed on demand
using a simple 8-bit parallel interface.


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