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AM29F200AB-70SIB データシート(PDF) 2 Page - Advanced Micro Devices |
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AM29F200AB-70SIB データシート(HTML) 2 Page - Advanced Micro Devices |
2 / 39 page 2 Am29F200A P R E L I M I NARY GENERAL DESCRIPTION The Am29F200A is a 2 Mbit, 5.0 Volt-only Flash mem- ory organized as 262,144 bytes or 131,072 words. The 8 bits of data appear on DQ0–DQ7; the 16 bits on DQ0– DQ15. The Am29F200A is offered in 44-pin SO and 48-pin TSOP packages. This device is designed to be programmed in-system with the standard system 5.0 volt VCC supply. A 12.0 volt VPP is not required for program or erase operations. The device can also be reprogrammed in standard EPROM programmers. The standard device offers access times of 55, 70, 9 0 , 12 0, an d 15 0 n s , al low i n g op era t io n of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 5.0 volt power sup- ply for both read and write functions. Internally gener- ated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Com- mands are written to the command register using stan- dard microprocessor write timings. Register contents serve as input to an internal state-machine that con- trols the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that auto- matically times the program pulse widths and verifies proper cell margin. Device erasure occurs by executing the erase com- mand sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already pro- grammed) before executing the erase operation. Dur- ing erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6/ DQ2 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The system can place the device into the standby mode. Power consumption is greatly reduced in this mode. AMD’s Flash technology combines years of Flash mem- ory manufacturing experience to produce the highest lev- els of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simulta- neously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. |
同様の部品番号 - AM29F200AB-70SIB |
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同様の説明 - AM29F200AB-70SIB |
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