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LS8292 データシート(PDF) 2 Page - LSI Computer Systems |
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LS8292 データシート(HTML) 2 Page - LSI Computer Systems |
2 / 13 page One of six stepping modes can be selected by two input pins: Full, 1/2, 1/4, 1/8, 1/16 and 1/32. An internal oscillator generates the system clock and sets the PWM period. The oscillator pin can also be driven by an external clock. Other available inputs are for step command, direction control, resetting to home position, disabling the H-bridge drives, SENSE input blanking delay control and fast to slow switching delay control in the mixed decay modes. INPUT/OUTPUT DESCRIPTION: XTLI, XTLO A crystal connected between these two pins sets the system clock frequency. Alternatively, XTLI pin can be driven by an external clock for providing the system clock. The PWM period Tpwm, is related to the system clock frequency as follows: Tpwm = 256/fc, where, fc is the system clock frequency applied at the XTLI input. M0, M1 M0 is a 3-state input amd M1 is a 2-state input; together they select the step mode as follows: Table 1 M1 M0 Step Mode 0 0 Full Step 1 0 1/2 Step 0 float 1/4 Step 1 float 1/8 Step 0 1 1/16 Step 1 1 1/32 Step RESET / When low, RESET/ input clears the step pointer to HOME position per table 4. This input has an internal pull-up resistor. STEP/ A low pulse at the STEP/ input causes the motor to advance one step forward or reverse. The step size is selected per Table 1. FWD When high, the FWD input causes the motor to step in the forward direction per incremental step sequence of Table 4. When low, the motor steps in the reverse direction per decremental step sequence of Table 4. EN/ When high, EN/ input causes all motor drive outputs to be disabled bringing INH1/, INH2/, PHA, PHB, PHC and PHD low. When ENABLE/ is low, all motor drive outputs are enabled. HOME/ HOME/ is an open drain output to indicate step0 per Table 4 with an active low. Vref Input for the chopper circuit DAC reference voltage. It regulates the peak motor winding current by regulating the PWM duty cycle. The DAC modifies the Vref input voltage for the current sensing comparators at every sequential motor step which can be estimated with the following equations: Vsens1 = | (Vref/7) x cos((90/32) x (n + 16))º | Vsens2 = | (Vref/7) x sin((90/32) x (n + 16))º | Where, n is the 1/32 column step number in Table 6. The sense resistors should satisfy the relation: Rs1 = Rs2 = Vref/(7 x Imax) where, Imax is the maximum motor winding current and Rs1 and Rs2 are the fractional-Ohm sense resistors in series with each phase of the H-bridge driver transistors. Vrefh Input for the holding torque reference voltage when the holding torque mode is enabled. The holding torque reference voltage should satisfy the relation: Vrefh = 7 x Rs1 x Imaxh = 7 x Rs2 x Imaxh, Where, Imaxh is the maximum winding current intended in the holding state and Rs1 and Rs2 are the fractional Ohm sense resistors in series with each phase of the H-bridge driver transistors. SENSE1, SENSE2 Inputs for motor winding current sense. A fractional-Ohm resistor connected in series with each of the H-bridge drivers produce SENSE1 and SENSE2 voltages. These voltages are compared with the DAC modulated reference voltages for generating the PWM phase or inhibit outputs. PHA, PHB, PHC, PHD Phase drive outputs for power stages. In a bipolar motor, PHA and PHB are used for one H-bridge while PHC and PHD are used for the other. In the slow-decay mode the phase outputs are chopped by means of the current sense comparators. In the fast-decay mode the phase outputs are kept enabled while the inhibit outputs are chopped. INH1/, INH2/ These outputs are active low inhibit controls for motor drive outputs. INH1/ controls driver stage using PHA and PHB outputs while INH2/ controls driver stage using PHC and PHD outputs. In the fast-decay mode inhibit outputs are chopped by means of the current sense comparators. In the slow-decay mode the inhibit outputs are enabled while the phase outputs are chopped. SYNC/ This open drain output produces a negative-going pulse occurring at the beginning of every PWM cycle which can be use to drive an external slope compensation circuit. Slope compensation may be useful at PWM duty cycle exceeding 50%, particularly in the fast-decay mode. TBLNK A resistor-capacitor pair connected to the TBLNK input controls the delay for which the sense input sampling is inhibited at the beginning of each PWM cycle. The delay is given by: Tblnk = 1.2 x RbCb Where, Rb and Cb are the resistor and the capacitor connected to the TBLNK pin. THLD A resistor-capacitor pair connected to this pin produces the holding torque initiation delay following a step command. Upon delay timeout the normal torque reference voltage Vref is switched out from the sense comparators, being replaced with the holding torque reference voltage Vrefh. The holding torque at lower dissipation prevails as long as the motor remains idle. The delay is given by: Thld = 1.4 x RhCh 8292-021811-2 |
同様の部品番号 - LS8292 |
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同様の説明 - LS8292 |
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