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74CBTLV3253D データシート(PDF) 1 Page - NXP Semiconductors |
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74CBTLV3253D データシート(HTML) 1 Page - NXP Semiconductors |
1 / 19 page 1. General description The 74CBTLV3253 provides a dual 1-of-4 high-speed multiplexer/demultiplexer with two common select inputs (S0, S1) and two output enable inputs (1OE, 2OE). The low ON resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise. When pin nOE = LOW, one of the four switches is selected (low-impedance ON-state) with pins S0 and S1. When pin nOE = HIGH, all switches are in the high-impedance OFF-state, independent of pins S0 and S1. To ensure the high-impedance OFF-state during power-up or power-down, nOE should be tied to the VCC through a pull-up resistor. The minimum value of the resistor is determined by the current-sinking capability of the driver. Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 2.3 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features and benefits Supply voltage range from 2.3 V to 3.6 V High noise immunity Complies with JEDEC standard: JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V CDM AEC-Q100-011 revision B exceeds 1000 V 5 switch connection between two ports Rail to rail switching on data I/O ports CMOS low power consumption Latch-up performance exceeds 250 mA per JESD78B Class I level A IOFF circuitry provides partial Power-down mode operation Multiple package options Specified from 40 Cto+85 C and 40 Cto+125 C 74CBTLV3253 Dual 1-of-4 multiplexer/demultiplexer Rev. 4 — 15 December 2011 Product data sheet |
同様の部品番号 - 74CBTLV3253D |
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同様の説明 - 74CBTLV3253D |
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