データシートサーチシステム |
|
AD7865AS-2 データシート(PDF) 11 Page - Analog Devices |
|
AD7865AS-2 データシート(HTML) 11 Page - Analog Devices |
11 / 19 page REV. B AD7865 –11– AD7865-3 Figure 4 shows the analog input section of the AD7865-3. The analog input range is ± 2.5 V on the VINxA input. The VINxB input can be left unconnected but if it is connected to a poten- tial then that potential must be AGND. AD7865-3 VINxA TRACK/ HOLD TO ADC REFERENCE CIRCUITRY TO INTERNAL COMPARATOR R1 R2 6k 2.5V REFERENCE VINxB VREF Figure 4. AD7865-3 Analog Input Structure For the AD7865-3, R1 = 4 k Ω and R2 = 4 kΩ. As a result, the VINxA input should be driven from a low impedance source. The resistor input stage is followed by the high input impedance stage of the track/hold amplifier. The designed code transitions take place midway between suc- cessive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs etc.) LSB size is given by the formula, 1 LSB = FSR/16384. Output coding is twos complement binary with 1 LSB = FSR/ 16384 = 5 V/16384 = 610.4 µV. The ideal input/output transfer function for the AD7865-3 is shown in Table III. Table III. Ideal Input/Output Code Table for the AD7865-3 Analog Input 1 Digital Output Code Transition +FSR/2 – 3/2 LSB 2 011 . . . 110 to 011 . . . 111 +FSR/2 – 5/2 LSB 011 . . . 101 to 011 . . . 110 +FSR/2 – 7/2 LSB 011 . . . 100 to 011 . . . 101 AGND + 3/2 LSB 000 . . . 001 to 000 . . . 010 AGND + 1/2 LSB 000 . . . 000 to 000 . . . 001 AGND – 1/2 LSB 111 . . . 111 to 000 . . . 000 AGND – 3/2 LSB 111 . . . 110 to 111 . . . 111 –FSR/2 + 5/2 LSB 100 . . . 010 to 100 . . . 011 –FSR/2 + 3/2 LSB 100 . . . 001 to 100 . . . 010 –FSR/2 + 1/2 LSB 100 . . . 000 to 100 . . . 001 NOTES 1FSR is full-scale range is 5 V, with V REF = 2.5 V. 21 LSB = FSR/16384 = 610.4 µV (±2.5 V—AD7865-3) with VREF = 2.5 V. SELECTING A CONVERSION SEQUENCE Any subset of the four channels VIN1 to VIN4 can be selected for conversion. The selected channels are converted in an ascending order. For example if the channel selection includes VIN4, VIN1 and VIN3 then the conversion sequence will be VIN1, VIN3 and then VIN4. The conversion sequence selection may be made by using either the hardware channel select input pins SL1 through SL4 (if H/S is tied low) or programming the channel select register (if H/S is tied high). A logic high on a hardware channel select pin (or logic one in the channel select register) when CONVST goes logic high, marks the associated analog input channel for inclusion in the conversion sequence. Figure 5 shows the arrangement used. The H/S SEL controls a multiplexer that selects the source of the conversion sequence information, i.e., from the hardware channel select pins (SL1 to SL4) or from the channel selection register. When a conversion is started the output from the multiplexer is latched until the end-of-the conversion sequence. The data bus bits DB0 to DB3 (DB0 representing Channel 1 through DB3 representing Chan- nel 4) are bidirectional and become inputs to the channel select register when RD is logic high and CS and WR are logic low. The logic state on DB0 to DB3 is latched into the channel select register when WR goes logic high. Figure 6 shows the loading sequence for channel selection using software control. When using software control to select the conversion sequence a write is only required each time the conversion sequence needs changing. This is because the channel select register will hold its information until different information is written to it. It should be noted that the hardware select Pins SL1 and SL2 are dual function. When H/S SEL is logic high (selecting the conversion sequence using software control) they take the func- tions CLK IN and INT/EXT CLK respectively. Therefore, the logic inputs on these pins must be set according to the type of operation required (see Using an External Clock). Also when H/S SEL is high, the SL3 and SL4 logic inputs have no function and can be tied either high or low, but should not be left floating. DATA BUS D0 D1 D2 D3 WR CS WR CHANNEL SELECT REGISTER SL1 SL2 SL3 SL4 HARDWARE CHANNEL SELECT PINS H/S TRANSPARENT WHILE WAITING FOR CONVST. LATCHED ON THE RISING EDGE OF CONVST AND DURING A CONVERSION SEQUENCE. MULTIPLEXER LATCH SEQUENCER SELECT INDIVIDUAL TRACK-AND-HOLDS FOR CONVERSION Figure 5. Channel Select Inputs and Registers RD WR CS DATA t16 t17 t14 t15 DATA IN t13 Figure 6. Channel Selection via Software Control |
同様の部品番号 - AD7865AS-2 |
|
同様の説明 - AD7865AS-2 |
|
|
リンク URL |
プライバシーポリシー |
ALLDATASHEET.JP |
ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |