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TSL1402R データシート(PDF) 3 Page - ams AG |
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TSL1402R データシート(HTML) 3 Page - ams AG |
3 / 17 page TSL1402R 256 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS041G − NOVEMBER 2011 2 r r Copyright E 2011, TAOS Inc. The LUMENOLOGY r Company www.taosinc.com Terminal Functions TERMINAL DESCRIPTION NAME NO. DESCRIPTION AO1 4 Analog output of section 1. AO2 8 Analog output of section 2. CLK 3 Clock. Clk controls charge transfer, pixel output, and reset. GND 5,12 Ground (substrate). All voltages are referenced to GND. NC 7, 9, 11, 14 No internal connection. SI1 2 Serial input (section 1). SI1 defines the start of the data-out sequence for section 1. SI2 10 Serial input (section 2). SI2 defines the start of the data-out sequence for section 2. SO1 13 Serial output (section 1). SO1 provides a signal to drive the SI2 input (in serial connection). SO2 6 Serial output (section 2). SO2 provides a signal to drive the SI input of another device for cascading or as an end-of-data indication. VDD 1 Supply voltage. Supply voltage for both analog and digital circuitry. Detailed Description Device operation (assumes serial connection) The sensor consists of 256 photodiodes, called pixels, arranged in a linear array. Light energy impinging on a pixel generates photocurrent, which is then integrated by the active integration circuitry associated with that pixel. During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity on that pixel and the integration time. The output and reset of the integrators is controlled by a 256-bit shift register and reset logic. An output cycle is initiated by clocking in a logic 1 on SI1. An internal signal, called Hold, is generated from the rising edge of SI1 and simultaneously transmitted to sections 1 and 2. This causes all 256 sampling capacitors to be disconnected from their respective integrators and starts an integrator reset period. As the SI pulse is clocked through the shift register, the charge stored on the sampling capacitors is sequentially connected to a charge-coupled output amplifier that generates a voltage on analog output AO. Simultaneously, during the first 18 clock cycles, all pixel integrators are reset, and the next integration cycle begins on the 19th clock. On the 128th clock rising edge, the SI pulse is clocked out on the SO1 pin (section 1) and becomes the SI pulse for section 2 (SI2). The rising edge of the 129th clock cycle terminates the SO1 pulse, and returns the analog output AO1 of section 1 to high-impedance state. Analog output AO2 now becomes the active output. As in section 2, SO2 is clocked out on the 256th clock pulse. Note that a 257th clock pulse is needed to terminate the SO2 pulse and return AO2 to the high-impedance state. If a minimum integration time is desired, the next SI pulse may be presented after a minimum delay of tqt (pixel charge transfer time) after the 257th clock pulse. |
同様の部品番号 - TSL1402R |
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同様の説明 - TSL1402R |
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