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UC2842DG4 データシート(PDF) 7 Page - Texas Instruments |
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UC2842DG4 データシート(HTML) 7 Page - Texas Instruments |
7 / 28 page www.ti.com OPEN-LOOP LABORATORY FIXTURE 4.7 kW 1 kW ERROR AMP ADJUST 4.7 kW 5 kW ISENSE ADJUST 2N2222 100 kW R1 1 2 3 4 8 7 6 5 COMP UC1842 VFB ISENSE RT / CT CT 0.1 mF 0.1 mF A 1 kW 1 W VREF VCC OUTPUT GROUND VREF VCC OUTPUT GROUND SHUTDOWN TECHNIQUES 8 3 1 kW 330 W SHUTDOWN 500 W To Current SENSE RESISTOR VREF ISENSE 1 SHUTDOWN COMP UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5 SLUS223C – APRIL 1997 – REVISED JUNE 2007 High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypas capacitors should be conected close to pin 5 in a single point ground. The transistor and 5k potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3. Shutdown of the UC1842 can be accomplished by two methods; either raise pin 3 above 1 V or pull pin 1 below a voltage two diode drops above ground. Either method causses the output of the PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at pin 1 and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SCR which will be reset by cycling VCC below the lower UVLO threshold. At this pint the reference turns off, allowing the SCR to reset. 7 Submit Documentation Feedback |
同様の部品番号 - UC2842DG4 |
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同様の説明 - UC2842DG4 |
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