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DAC1220E データシート(PDF) 6 Page - Burr-Brown (TI) |
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DAC1220E データシート(HTML) 6 Page - Burr-Brown (TI) |
6 / 14 page 6 ® DAC1220 Self-Calibration A self-calibration is performed after the bits “01” have been written to the Command Register Operation Mode bits (MD1 through MD0) and a “1” has been written to the Command Register sample-and-hold bit (SH). This initiates a self-calibration on the next clock cycle. The offset correc- tion code is determined by a repeated sequence of auto- zeroing the calibration comparator to the offset reference and then comparing the DAC output to the offset reference value. The end result is then averaged, Offset Two’s Comple- ment adjusted, and placed in the OCR. The gain correction is done in a similar fashion except the correction is done against VREF to eliminate common-mode errors. The FCR result represents the gain code and is not Offset Two’s Complement adjusted. The calibration function takes between 300ms and 500ms to complete (for fXIN = 2.5MHz). Once calibration is initiated, further writing of register bits is disabled until calibration completes. The status of calibration can be verified by reading the status of the Command Register Operation Mode bits (MD1 through MD0). These bits will return to normal mode “00” when calibration is complete. Self-calibration can be done with the output isolated or connected. This is done by setting (output connected) or clearing (output isolated) the CALPIN bit in the CMR register. Output Mode The DAC1220 can operate in either 16-bit mode or 20-bit mode. The mode is determined by setting (20-bit) or clearing (16-bit) the RES bit in the CMR register. The output of the DAC1220 can be synchronously reset. By setting the CLR bit in the CMR, the data input register is cleared to zero. This will result in an output of 0V when DF = 1 or VREF when DF = 0, assuming no calibration errors. The settling time is determined by the DISF, RES, and ADPT bits of the command register. The default state of DISF = 0 and ADPT = 0 enables fast settling, unless the output step is small ( ≈ 40mV). However, the DAC1220 can be forced to always use fast settling if the ADPT bit is set to 1. If DISF is set to 1, all fast settling is disabled. The SH bit of the CMR register determines if C2 is internally connected to VREF. By clearing the SH bit, C2 is discon- nected from VREF. The CRST bit of the CMR register can be used to reset the offset and calibration registers. By setting the CRST bit, the contents of the calibration register are reset to 0. REFERENCE INPUT The reference input voltage of 2.5V can be directly con- nected to VREF. The recommended reference circuit for the DAC1220 is shown in Figure 2. FIGURE 2. Recommended External Voltage Reference Circuit for Best Low Noise Operation with the DAC1220. + OPA336 2 7 3 1 6 4 +5V +5V 100k Ω REF1004-2.5 10k Ω 0.10 µF 10 µF 0.1 µF + 10 µF 0.10 µF To V REF Pin 100 Ω |
同様の部品番号 - DAC1220E |
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同様の説明 - DAC1220E |
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