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CAT28C257HT13-15T データシート(Datasheet) 5 Page - Catalyst Semiconductor

部品番号. CAT28C257HT13-15T
部品情報  256K-Bit CMOS PARALLEL E2PROM
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メーカー  CATALYST [Catalyst Semiconductor]
ホームページ  http://www.catalyst-semiconductor.com
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Advanced
CAT28C257
5
Doc. No. 25073-00 2/98
Note:
(1)
This parameter is tested initially and after a design or process change that affects the parameter.
(2)
Input rise and fall times (10% and 90%) < 10 ns.
(3)
A write pulse of less than 20ns duration will not initiate a write cycle.
(4)
A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
however a transition from HIGH to LOW within tBLC max. stops the timer.
5096 FHD F04
Figure 1. A.C. Testing Input/Output Waveform(2)
1.3V
DEVICE
UNDER
TEST
1N914
3.3K
CL = 100 pF
OUT
CL INCLUDES JIG CAPACITANCE
Figure 2. A.C. Testing Load Circuit (example)
INPUT PULSE LEVELS
REFERENCE POINTS
2.0 V
0.8 V
2.4 V
0.45 V
5096 FHD F03
A.C. CHARACTERISTICS, Write Cycle
VCC=5V
±10%, unless otherwise specified
28C257-90
28C257-12
28C257-15
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Units
tWC
Write Cycle Time
5
5
5
ms
tAS
Address Setup Time
0
0
0
ns
tAH
Address Hold Time
50
50
50
ns
tCS
CE Setup Time
0
0
0
ns
tCH
CE Hold Time
0
0
0
ns
tCW(3
CE Pulse Time
100
100
100
ns
tOES
OE Setup Time
0
0
0
ns
tOEH
OE Hold Time
0
0
0
ns
tWP(3)
WE Pulse Width
100
100
100
ns
tDS
Data Setup Time
50
50
50
ns
tDH
Data Hold Time
0
0
0
ns
tINIT(1)
Write Inhibit Period After Power-up
5
10
5
10
5
10
ms
tBLC(1)(4)
Byte Load Cycle Time
0.1
100
0.1
100
0.1
100
µs




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