データシートサーチシステム |
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ADV7123SCP170EP-RL データシート(PDF) 6 Page - Analog Devices |
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ADV7123SCP170EP-RL データシート(HTML) 6 Page - Analog Devices |
6 / 12 page ADV7123-EP Rev. 0 | Page 6 of 12 t3 t1 t4 t8 t2 t6 t7 t5 CLOCK DIGITAL INPUTS (R9 TO R0, G9 TO G0, B9 TO B0, SYNC, BLANK) ANALOG INPUTS (IOR, IOR, IOG, IOG, IOB, IOB) NOTES 1. OUTPUT DELAY ( t6) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF CLOCKTO THE 50% POINT OF FULL-SCALE TRANSITION. 2. OUTPUT RISE/FALL TIME ( t7) MEASURED BETWEEN THE 10% AND 90% POINTS OF FULL-SCALE TRANSITION. 3. TRANSITION TIME ( t8) MEASURED FROM THE 50% POINT OF FULL-SCALE TRANSITION TO WITHIN 2% OF THE FINAL OUTPUT VALUE. Figure 2. Timing Diagram |
同様の部品番号 - ADV7123SCP170EP-RL |
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同様の説明 - ADV7123SCP170EP-RL |
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