データシートサーチシステム |
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CS5101EDW16 データシート(PDF) 4 Page - Cherry Semiconductor Corporation |
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CS5101EDW16 データシート(HTML) 4 Page - Cherry Semiconductor Corporation |
4 / 7 page 4 PACKAGE PIN # PIN SYMBOL FUNCTION Package Pin Description 14L PDIP 16L SO Wide 1 1 SYNC Synchronization input. 22 VCC Logic supply (10V to 45V). 33 VREF 5.0V voltage reference. 4 LGnd Logic level ground (Analog and digital ground tied). 56 VFB Error amplifier inverting input. 6 7 COMP Error amplifier output and compensation. 7 8 RAMP RAMP programmable with the external capacitor. 8 9 IS+ Current sense amplifier non-inverting input. 9 10 IS- Current sense amplifier inverting input. 10 11 IS COMP Current sense amplifier compensation and output. 11 12, 13 PGnd Power ground. 12 14 VG External power switch gate drive. 13 15 VC Output power stage supply voltage (8V to 75V). 14 16 VD External FET DRAIN Voltage Monitor. 5 AGnd Analog Ground. 4 DGnd Digital Ground. Circuit Description COMP RAMP LGnd SYNC LATCH Q VREF PGnd IS COMP VD 5V VC VG IS Q1 Q2 REF_OK G1 G2 I = 200 mA VFB 2.5V 2V Q3 + Ð SYNC VCC_OK + Ð VCC S R PWM + Ð 4.5V/4.4V 1.65V + Ð RAMP + + Ð Ð + Ð EA + Ð BUF + Ð IS+ IS- 1.5V 0.7V Q4 + Ð SLEEP VCC + Ð REF UVL OK 0.7V 8V/7V 2.4V 24.6k 5V 5V 5V 5V 5V 5V VCC 10k 10k 5V 5V + Ð + Ð + Ð + Ð + Ð + Ð + Ð + Ð + Ð VCC + VC Q Block Diagram |
同様の部品番号 - CS5101EDW16 |
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同様の説明 - CS5101EDW16 |
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