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CS5165GDWR16 データシート(PDF) 2 Page - Cherry Semiconductor Corporation |
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CS5165GDWR16 データシート(HTML) 2 Page - Cherry Semiconductor Corporation |
2 / 19 page Absolute Maximum Ratings Pin Symbol Pin Name VMAX VMIN ISOURCE ISINK 2 PACKAGE PIN # PIN SYMBOL FUNCTION Package Pin Description VCC IC Power Input 16V -0.3V N/A 1.5A Peak 200mA DC SS Soft Start Capacitor 6V -0.3V 200µA 10µA COMP Compensation Capacitor 6V -0.3V 10mA 1mA VFB Voltage Feedback Input 6V -0.3V 10µA 10µA COFF Off-Time Capacitor 6V -0.3V 1mA 50mA VID0-4 Voltage ID DAC Inputs 6V -0.3V 1mA 10µA GATE(H) High-Side FET Driver 16V -0.3V 1.5A Peak; 1.5A Peak; 200mA DC 200mA DC GATE(L) Low-Side FET Driver 16V -0.3V 1.5A Peak; 1.5A Peak; 200mA DC 200mA DC ENABLE Enable Input 6V -0.3V 100µA 1mA PWRGD Power-Good Output 6V -0.3V 10µA 30mA PGnd Power Ground 0V 0V 1.5A Peak N/A 200mA DC LGnd Logic Ground 0V 0V 100mA N/A Operating Junction Temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° to 150°C Lead Temperature Soldering: Reflow (SMD styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 sec max. above 183°C, 230°C Peak Storage Temperature Range, TS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C ESD Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV 1,2,3,4,6 VID0 -VID4 Voltage ID DAC inputs. These pins are internally pulled up to 5V if left open. VID4 selects the DAC range. When VID4 is high (logic one), the Error Amp ref- erence range is 2.14V to 3.54V with 100mV increments. When VID4 is low (logic zero), the Error amp reference voltage is 1.34V to 2.09V with 50mV increments. 5 SS Soft Start Pin. A capacitor from this pin to LGnd sets the Soft Start and fault timing. 7 COFF Off-Time Capacitor Pin. A capacitor from this pin to LGnd sets both the nor- mal and extended off time. 8 ENABLE Output Enable Input. This pin is internally pulled up to 1.8V. A logic Low ( < 0.8V) on this pin disables operation and places the CS5165 into a low cur- rent sleep mode. 9 VCC Input Power Supply Pin. 10 GATE(H) High Side Switch FET driver pin. 11 PGnd High Current ground for the GATE(H) and GATE(L) pins. 12 GATE(L) Low Side Synchronous FET driver pin. 13 PWRGD Power Good Output. Open collector output drives low when VFB is out of regulation. Active when ENABLE input is low 14 LGnd Reference ground. All control circuits are referenced to this pin. 15 COMP Error Amp output. PWM Comparator reference input. A capacitor to LGnd provides Error Amp compensation. 16 VFB Error Amp, PWM Comparator, and Low VFB Comparator feedback input. |
同様の部品番号 - CS5165GDWR16 |
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同様の説明 - CS5165GDWR16 |
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