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CS8271YD8 データシート(PDF) 3 Page - Cherry Semiconductor Corporation |
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CS8271YD8 データシート(HTML) 3 Page - Cherry Semiconductor Corporation |
3 / 6 page 3 Package Pin Description PACKAGE PIN # PIN SYMBOL FUNCTION PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics: VOUT + 1V ² VIN ² 30V, 5V ² VOUT ² 12V, IOUT = 10mA, -40¡ ² TA ² 125¡, -40¡ ² TJ ² 150¡, VENABLE = 0V; unless otherwise specified. The output voltage of the CS8271 is adjustable to any value between the reference voltage on the Adj pin, (1.272V Typ.) and the maximum input voltage minus the dropout voltage. To adjust the output voltage, a pair of external resistors R1 and R2 are connected as shown in Figure 1. The equation for the output voltage is VOUT = VREF x+ IAdj x R1 where Vref is the typical reference voltage and IAdj is the adjust pin bias current. This is usually 500nA maximum. Figure 1: Output Voltage Adjustment. Adj CS8271 VOUT R1 VOUT R2 VREF ) R1 + R2 R2 ( Output Voltage Adjustment Circuit Description 8L SOIC & PDIP 1VOUT 100mA output; adjustable from 5V to 12V. 2 Gnd Ground. 3, 6, 7 NC No Connection. 4 Adj Resistor divider from VOUT to Adj, sets output voltage. 5 Logic level switch, when HIGH, regulator is in sleep mode. 8VIN Input voltage. ENABLE s Enable Threshold 1.15 2.0 2.6 V Enable Input Current VENABLE = 2.6V 10 20 µA VENABLE = 5V 35 50 µA s Adjustment Pin R1: Feedback resistor between VOUT and Adjust, R2: Adjust resistor to ground. Reference Voltage 100µA ² IOU T² 100mA 1.246 1.272 1.297 V Adjustment Pin Current IAdj = - 20 500 nA Note 1: Guaranteed by design, not 100% tested in production. (VOUT - VREF) R1 VREF R2 ENABLE |
同様の部品番号 - CS8271YD8 |
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同様の説明 - CS8271YD8 |
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