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CS4225-YU データシート(PDF) 10 Page - Cirrus Logic |
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CS4225-YU データシート(HTML) 10 Page - Cirrus Logic |
10 / 30 page FUNCTIONAL DESCRIPTION Overview The CS4225 has 2 channels of 16-bit analog-to- digital conversion and 4 channels of 16-bit digital-to-analog conversion. An auxiliary 12-bit ADC is also provided. The ADCs and the DACs are delta-sigma type converters. The ADC inputs have adjustable input gain, while the DAC out- puts have adjustable output attenuation. Digital audio data for the DACs and from the ADCs is communicated over a serial port. Sepa- rate pins for input and output data are provided, allowing concurrent writing to and reading from the device. Control for the functions available on the CS4225 are communicated over a serial mi- crocontroller style interface, or may be set via dedicated mode pins. Figure 1 shows the recom- mended connection diagram for the CS4225. Analog Inputs Line Level Inputs AIN1R, AIN1L, AIN2R, AIN2L, AIN3R, AIN3L and AINAUX are the line level input pins (See Figure 1). These pins are internally biased to the CMOUT voltage (nominally 2.1V). A 1 µF DC blocking capacitor allows signals centered around 0V to be input. Figure 2 shows an op- tional dual op amp buffer which combines level shifting with a gain of 0.5 to attenuate the stand- ard line level of 2Vrms to 1Vrms. The CMOUT reference level is used to bias the op amps to approximately one half the supply voltage. Series DC blocking capacitors eliminate the con- tribution of signal offset to the A/D converters. The CS4225 offset calibration scheme yields minimum DC offset values assuming that the in- puts are AC coupled (DC blocking capacitor present). If a DC blocking capacitor is not used, a greater DC offset will occur. This offset could be as high as + 70 codes, with no gain. The input pair for the 16-bit ADCs is selected by IS0 and IS1, which are accessible in the Input Selection Byte in software mode or dedicated pins in the hardware mode. Antialiasing filters follow the input mux, providing antialiasing for the input channels. These filters consist of inter- nal resistors and external capacitors attached to the CR and CL pins. The CR and CL capacitors must be low voltage coefficient type, such as NPO. The analog signal is input to the 12-bit ADC via the AINAUX pin. An antialiasing filter of 150 Ω with 0.01 µF to ground is required (See Figure 1) along with a series DC blocking capacitor. The AINAUX signal is normally routed to the 12-bit ADC. This signal may also be routed to the Left 16-bit ADC (replacing the selected left input), under control of the AIM bit in the 12-bit ADC Mode Byte. In this mode, the input antialiasing filters and gain adjustment operates on the AINAUX signal. Adjustable Input Gain The signals from the line inputs are routed to a programmable gain circuit which provides up to + _ 56 pF 10 k 20 k + _ 10 k 56 pF 5 k 20 k Line In Line In Right Left CMOUT AINxR AINxL Example Op-Amps are MC34074 0.47 uF 1.0 uF 0.47 uF 1.0 uF 1.0 uF 1.0 uF Op-amps are run from VA+ (+5V) and AGND. Figure 2 - Optional Line Input Buffer CS4225 10 DS86PP8 |
同様の部品番号 - CS4225-YU |
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同様の説明 - CS4225-YU |
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