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CDCV850IDGG データシート(PDF) 8 Page - Texas Instruments

部品番号 CDCV850IDGG
部品情報  2.5-V PHASE LOCK LOOP CLOCK DRIVER WITH 2-LINE SERIAL INTERFACE
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
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CDCV850IDGG データシート(HTML) 8 Page - Texas Instruments

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CDCV850
2.5-V PHASE LOCK LOOP CLOCK DRIVER
WITH 2-LINE SERIAL INTERFACE
SCAS647D − OCTOBER 2000 − REVISED APRIL 2013
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
2-line serial interface
2-line serial interface slave address
A7
A6
A5
A4
A3
A2
A1
R/W
1
1
0
1
0
0
1
0
Writing to the device is accomplished by sequentially sending the device address D2H, the dummy bytes
(command code and the number of bytes), and the data bytes. This sequence is illustrated in the following
tables:
Start Bit
Slave Address
R/W
Ack
Ack
Command Code
Byte Count = N
Ack
Data Byte 0
Ack
Data Byte 1
Ack
Data Byte N
Ack
Stop
1 bit
1 bit
1 bit
7 bits
8 bits
1 bit
8 bits
1 bit
8 bits
1 bit
8 bits
1 bit
1 bit
8 bits
1 bit
2-line serial interface configuration command bitmap
The 2-line serial command bytes are used to control the output clock pairs (Y[0:9], Y[0:9]). The output clock pairs
are enabled after power up. During normal operation, the clock pairs can be disabled (set Hi-Z) or enabled
(running) by writing the corresponding bit to the data bytes in the following tables:
Byte 0: Enable/Disable Register
(H = Enable, L = Disable)
Byte 1: Enable/Disable Register
(H = Enable, L = Disable)
BIT
PINS
INITIAL
VALUE
DESCRIPTION
BIT
PINS
INITIAL
VALUE
DESCRIPTION
7
3, 2
H
Y0, Y0
7
29, 30
H
Y8, Y8
6
5, 6
H
Y1, Y1
6
27, 26
H
Y9, Y9
5
10, 9
H
Y2, Y2
5
L
Reserved
4
20, 19
H
Y3, Y3
4
L
Reserved
3
22, 23
H
Y4, Y4
3
L
Reserved
2
46, 47
H
Y5, Y5
2
L
Reserved
1
44, 43
H
Y6, Y6
1
L
Reserved
0
39, 40
H
Y7, Y7
0
L
Reserved


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