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SL16020DCT データシート(PDF) 6 Page - Silicon Laboratories |
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SL16020DCT データシート(HTML) 6 Page - Silicon Laboratories |
6 / 10 page Rev 2.2, August 1, 2010 Page 6 of 10 SL16020DC External Resistor Dividers for 3-Level Logic Implementation 3-Level Logic HIGH=VDD VDD 5K Ω SSEL0 or SSEL1 INPUT 7/3 3-Level Logic LOW=VSS VSS 5K Ω SSEL0 or SSEL1 INPUT 7/3 HIGH (H) = VDD MIDDLE (M) = VDD/2 LOW (L) = VSS 3-Level Logic Middle=VDD/2 VSS VDD 5K Ω 5K Ω SSEL0 or SSEL1 INPUT 7/3 Figure 3. FSEL0 and FSEL1 Spread % Selection Logic Note: SSEL0 and SSEL1 pins use 3-Level L(LOW) = VSS, M(MIDDLE)=VDD/2 and H(HIGH) = VDD 3-Level logic to provide 9 spread % values at SSCLK (pin 5) as given in Table 5. Use 5k Ω/5kΩ external resistor dividers at SSEL0 and SSEL1 pins from VDD to VSS to obtain VDD/2 for M=VDD/2 Logic level as shown above in Figure 3. |
同様の部品番号 - SL16020DCT |
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同様の説明 - SL16020DCT |
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