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FIN1218 データシート(PDF) 9 Page - Fairchild Semiconductor |
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FIN1218 データシート(HTML) 9 Page - Fairchild Semiconductor |
9 / 20 page © 2003 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 9 Transmitter AC Electrical Characteristics (Continued) Symbol Parameter Conditions Min. Typ. Max. Units Transmitter Output Data Jitter (f=85 MHz, FIN1217 only) (12) tTPPB0 Transmitter Output Pulse Position of Bit 0 Figure 20 7 f 1 a × = -0.2 0 0.2 ns tTPPB1 Transmitter Output Pulse Position of Bit 1 a-0.2 a a+0.2 ns tTPPB2 Transmitter Output Pulse Position of Bit 2 2a-0.2 2a 2a+0.2 ns tTPPB3 Transmitter Output Pulse Position of Bit 3 3a-0.2 3a 3a+0.2 ns tTPPB4 Transmitter Output Pulse Position of Bit 4 4a-0.2 4a 4a+0.2 ns tTPPB5 Transmitter Output Pulse Position of Bit 5 5a-0.2 5a 5a+0.2 ns tTPPB6 Transmitter Output Pulse Position of Bit 6 6a-0.2 6a 6a+0.2 ns tJCC Transmitter Clock Out Jitter, Cycle-to cycle Figure 23 f=40MHz 350 370 ps f=65MHz 210 230 f=85MHz FIN1217 only 110 150 tTPLLS Transmitter Phase Lock Loop Set Time (13) Figure 15 (12) 10.0 ms Notes: 11. Outputs of all transmitters stay in 3-STATE until power reaches 2V. Clock and data output begins to toggle 10ms after VCC reaches 3V and /PwrDn pin is above 1.5V. 12. This output data pulse position works for both transmitters with 21 TTL inputs, except the LVDS output bit mapping difference (see Figure 19). Figure 20 shows the skew between the first data bit and clock output. A two-bit cycle delay is guaranteed when the MSB is output from transmitter. 13. This jitter specification is based on the assumption that PLL has a reference clock with cycle-to-cycle input jitter of less than 2ns. |
同様の部品番号 - FIN1218 |
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同様の説明 - FIN1218 |
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