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TPD4E001-Q1 データシート(PDF) 3 Page - Texas Instruments |
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TPD4E001-Q1 データシート(HTML) 3 Page - Texas Instruments |
3 / 14 page TPD4E001-Q1 www.ti.com SLLSEG0C – MARCH 2013 – REVISED JUNE 2013 THERMAL INFORMATION TPD4E001-Q1 THERMAL METRIC(1) DBV UNIT 6 PINS θJA Junction-to-ambient thermal resistance(2) 202.1 °C/W θJCtop Junction-to-case (top) thermal resistance(3) 146.2 °C/W θJB Junction-to-board thermal resistance(4) 47.1 °C/W ψJT Junction-to-top characterization parameter(5) 37.6 °C/W ψJB Junction-to-board characterization parameter(6) 46.7 °C/W θJCbot Junction-to-case (bottom) thermal resistance(7) N/A °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). (6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). (7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer Electrical Characteristics VCC = 5 V ± 10%, TA = –40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT VCC Supply voltage 0.9 5.5 V ICC Supply current 1 200 nA VF Diode forward voltage IF = 10 mA 0.65 0.95 V VBR Breakdown voltage IBR = 10 mA 11 V VCLAM Surge strike(2) on IO pin, GND pin Clamping voltage Positive transients 16 V P grounded, VCC = 5.5 V, IPP = 5.5 A VRWM Reverse standoff voltage IO pin to GND pin 5.5 V Ii/o Channel leakage current Vi/o = GND to VCC ±10 nA Ci/o Channel input capacitance VCC = 5 V, bias of VCC/2 1.5 pF (1) Typical values are at VCC = 5 V and TA = 25°C. (2) Non-repetitive current pulse 8/20 µs exponentially decaying waveform according to IEC 61000-4-5. ESD Protection PARAMETER TYP UNIT HBM ±15 kV IEC 61000-4-2 contact discharge ±8 kV IEC 61000-4-2 air-gap discharge ±15 kV Peak pulse current, IPP (Tp = 8/20 µs) (1) 5.5 A Peak pulse power, PPP (Tp = 8/20 µs) (1) 100 W (1) Non-repetitive current pulse 8/20 µs exponentially decaying waveform according to IEC 61000-4-5. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPD4E001-Q1 |
同様の部品番号 - TPD4E001-Q1_14 |
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同様の説明 - TPD4E001-Q1_14 |
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