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LM3421 データシート(PDF) 3 Page - Texas Instruments

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部品番号 LM3421
部品情報  N-Channel Controllers for Constant Current LED Drivers
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LM3421, LM3421-Q1
LM3423, LM3423-Q1
www.ti.com
SNVS574D – JULY 2008 – REVISED SEPTEMBER 2011
PIN DESCRIPTIONS (continued)
LM3423
LM3421
Name
Description
Function
Connect a PWM signal for dimming as detailed in the PWM
Dimming Input /
DIMMING section and/or a resistor divider from VIN to program input
8
8
nDIM
Under-Voltage Protection
under-voltage lockout (UVLO). Turn-on threshold is 1.24V and
hysteresis for turn-off is provided by 23 µA current source.
Connect to pull-up resistor from VIN and N-channel MosFET open
9
-
FLT
Fault Flag
drain output is high when a fault condition is latched by the timer.
Connect a capacitor to AGND to set the time delay before a sensed
10
-
TIMR
Fault Timer
fault condition is latched.
Connect to pull-up resistor from VIN and N-channel MosFET open
11
-
LRDY
LED Ready Flag
drain output pulls down when the LED current is not in regulation.
Connect to AGND if dimming with a series P-channel MosFET or
12
-
DPOL
Dim Polarity
leave open when dimming with series N-channel MosFET.
13
9
DDRV
Dim Gate Drive Output
Connect to the gate of the dimming MosFET.
Connect to AGND through the DAP copper pad to provide ground
14
10
PGND
Power Ground
return for GATE and DDRV.
15
11
GATE
Main Gate Drive Output
Connect to the gate of the main switching MosFET.
16
12
VCC
Internal Regulator Output
Bypass with 2.2 µF–3.3 µF ceramic capacitor to PGND.
Connect to the drain of the main N-channel MosFET switch for RDS-
17
13
IS
Main Switch Current Sense
ON sensing or to a sense resistor installed in the source of the same
device.
Connect the low side of all external resistor dividers (VIN UVLO, OVP)
18
14
RPD
Resistor Pull Down
to implement “zero-current” shutdown.
Connect through a series resistor to the positive side of the LED
19
15
HSP
LED Current Sense Positive
current sense resistor.
Connect through a series resistor to the negative side of the LED
20
16
HSN
LED Current Sense Negative
current sense resistor.
Star ground, connecting AGND and PGND. For thermal
DAP (21)
DAP (17)
DAP
Thermal PAD on bottom of IC
considerations please refer to (1).
(1)
Junction-to-ambient thermal resistance is highly board-layout dependent. The numbers listed in the table are given for an reference
layout wherein the 16L TSSOP package has its EP pad populated with 9 vias and the 20L TSSOP has its EP pad populated with 12
vias. In applications where high maximum power dissipation exists, namely driving a large MosFET at high switching frequency from a
high input voltage, special care must be paid to thermal dissipation issues during board design. In high-power dissipation applications,
the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum
operating junction temperature (TJ-MAX-OP = 125°C for Q1, or 150°C for Q0), the maximum power dissipation of the device in the
application (PD-MAX), and the junction-to ambient thermal resistance of the package in the application (θJA), as given by the following
equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). In most applications there is little need for the full power dissipation capability of this
advanced package. Under these circumstances, no vias would be required and the thermal resistances would be 104 °C/W for the 16L
TSSOP and 86.7 °C/W for the 20L TSSOP. It is possible to conservatively interpolate between the full via count thermal resistance and
the no via count thermal resistance with a straight line to get a thermal resistance for any number of vias in between these two limits.
Copyright © 2008–2011, Texas Instruments Incorporated
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Product Folder Links: LM3421 LM3421-Q1 LM3423 LM3423-Q1


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