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TSB43AB22 データシート(PDF) 3 Page - Texas Instruments

部品番号 TSB43AB22
部品情報  Integrated 1394a-2000 OHCI PHY/Link-Layer Controller
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
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TSB43AB22 データシート(HTML) 3 Page - Texas Instruments

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Not Recommended for New Designs
TSB43AB22
SLLA208 – JUNE 2006
The line drivers in the TSB43AB22 device operate in a high-impedance current mode and are designed to work
with external 112-
Ω line-termination resistor networks in order to match the 110-Ω cable impedance. One
network is provided at each end of a twisted-pair cable. Each network is composed of a pair of series-connected
56-
Ω resistors. The midpoint of the pair of resistors that is directly connected to the TPA terminals is connected
to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly connected to
the TPB terminals is coupled to ground through a parallel R-C network with recommended values of 5 k
Ω and
220 pF. The values of the external line-termination resistors are designed to meet the standard specifications
when connected in parallel with the internal receiver circuits. An external resistor connected between the R0 and
R1 terminals sets the driver output current and other internal operating currents. This current-setting resistor has
a value of 6.34 k
Ω± 1%.
When the power supply of the TSB43AB22 device is off and the twisted-pair cables are connected, the
TSB43AB22 transmitter and receiver circuitry present a high impedance to the cable and do not load the
TPBIAS voltage at the other end of the cable.
When the device is in a low-power state (for example, D2 or D3) the TSB43AB22 device automatically enters a
low-power mode if all ports are inactive (disconnected, disabled, or suspended). In this low-power mode, the
TSB43AB22 device disables its internal clock generators and also disables various voltage and current
reference circuits, depending on the state of the ports (some reference circuitry must remain active in order to
detect new cable connections, disconnections, or incoming TPBIAS, for example). The lowest power
consumption (the ultralow-power sleep mode) is attained when all ports are either disconnected or disabled with
the port interrupt enable bit cleared.
The TSB43AB22 device exits the low-power mode when bit 19 (LPS) in the host controller control register at
OHCI offset 50h/54h is set to 1 or when a port event occurs which requires that the TSB43AB22 device to
become active in order to respond to the event or to notify the LLC of the event (for example, incoming bias is
detected on a suspended port, a disconnection is detected on a suspended port, or a new connection is
detected on a nondisabled port). When the TSB43AB22 device is in the low-power mode, the internal
49.153-MHz clock becomes active (and the integrated PHY layer becomes operative) within 2 ms after bit 19
(LPS) in the host controller control register at OHCI offset 50h/54h is set to 1.
The TSB43AB22 device supports hardware enhancements to better support digital video (DV) and MPEG data
stream reception and transmission. These enhancements are enabled through the isochronous receive digital
video enhancements register at OHCI offset A88h. The enhancements include automatic timestamp insertion for
transmitted DV and MPEG-formatted streams and common isochronous packet (CIP) header stripping for
received DV streams.
The CIP format is defined by the IEC 61883-1:1998 specification. The enhancements to the isochronous data
contexts are implemented as hardware support for the synchronization timestamp for both DV and MPEG CIP
formats. The TSB43AB22 device supports modification of the synchronization timestamp field to ensure that the
value inserted via software is not stale—that is, the value is less than the current cycle timer when the packet is
transmitted.
NOTE:
This product is for high-volume PC applications only. For a complete datasheet or
more information contact support@ti.com.
3
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