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TSB41BA3B-EP データシート(PDF) 2 Page - Texas Instruments

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部品番号 TSB41BA3B-EP
部品情報  IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
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TSB41BA3B-EP データシート(HTML) 2 Page - Texas Instruments

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TSB41BA3BEP
IEEE 1394b THREEPORT CABLE TRANSCEIVER/ARBITER
SGLS362—MAY 2006
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
description/ordering information
The TSB41BA3B-EP provides the digital and
analog transceiver functions needed to imple-
ment a three-port node in a cable-based IEEE
1394 network. Each cable port incorporates two
differential line transceivers. The transceivers
include circuitry to monitor the line conditions as
needed for determining connection status, for
initialization and arbitration, and for packet
reception and transmission. The TSB41BA3B-EP
interfaces with a link-layer controller (LLC), such
as the TSB82AA2, TSB12LV21, TSB12LV26,
TSB12LV32,
TSB42AA4,
TSB42AB4,
TSB12LV01B, or TSB12LV01C. It can also be
connected via cable port to an integrated 1394
Link + PHY layer such as the TSB43AB2.
The TSB41BA3B-EP is powered by a single 3.3-V supply. The core voltage supply is supplied by an internal
voltage regulator to the PLLVDD-CORE and DVDD-CORE terminals. To protect the phase-locked loop (PLL)
from noise, the PLLVDD-CORE terminals must be separately decoupled from the DVDD-CORE terminals. The
PLLVDD-CORE terminals are decoupled with 1-
µF and smaller decoupling capacitors and the DVDD-CORE
terminals are separately decoupled with 1-
µF and smaller decoupling capacitors. The separation between
DVDD-CORE and PLLVDD-CORE must be implemented by separate power supply rails or planes.
The TSB41BA3B-EP may be powered by dual supplies, a 3.3-V supply for I/O and a core voltage supply. The
core voltage supply to the PLLVDD-CORE and DVDD-CORE terminals must meet the requirements in the
recommended operating conditions section of this data sheet. The PLLVDD-CORE terminals must be
separated from the DVDD-CORE terminals, the PLLVDD-CORE terminals are decoupled with 1-
µF and smaller
decoupling capacitors, and the DVDD-CORE terminals separately decoupled with 1-
µF and smaller decoupling
capacitors. The separation between DVDD-CORE and PLLVDD-CORE can be implemented by separate power
supply rails, or by a single power supply rail, where the DVDD-CORE and PLLVDD-CORE are separated by
a filter network to keep noise from the PLLVDD-CORE supply.
The TSB41BA3B-EP requires an external 49.152-MHz crystal to generate a reference clock. The external clock
drives an internal phase-locked loop (PLL), which generates the required reference signal. This reference signal
provides the clock signals that control transmission of the outbound encoded information. A 49.152-MHz clock
signal is supplied by the PHY to the associated LLC for synchronization of the two devices and is used for
resynchronization of the received data when operating the PHY-link interface in compliance with the IEEE
1394a-2000 standard. A 98.304-MHz clock signal is supplied by the PHY to the associated LLC for
synchronization of the two devices when operating the PHY-link interface in compliance with the
IEEE 1394b-2002 standard. The power down (PD) function, when enabled by asserting the PD terminal high,
stops operation of the PLL.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40
°C to 110°C
HTQFP − PFP
TSB41BA3BTPFPEP
TSB41B3BTEP
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
D Supports Connection to CAT5 Cable
Transceiver by Allowing Ports to be Forced
to Beta-Only S100 Mbps
D Supports Connection to S200 Plastic
Optical Fiber Transceivers by Allowing
Ports to be Forced to 1394b Beta-Only S200
Mbps and Beta-Only S100 Mbps
D Optical Signal Detect Input for All Ports in
Beta Mode Enables Connection to Optical
Transceivers
D Supports Use of 1394a Connectors by
Allowing Ports 1 and 2 to Be Forced to
1394a-Only Mode


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