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ADC10D020CIVSX データシート(PDF) 8 Page - Texas Instruments |
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ADC10D020CIVSX データシート(HTML) 8 Page - Texas Instruments |
8 / 40 page ADC10D020 SNAS143D – SEPTEMBER 2001 – REVISED MARCH 2013 www.ti.com Converter Electrical Characteristics (continued) The following specifications apply for VA = VD = VDR = +3.0 VDC, VREF = 1.0 VDC, GAIN = OF = 0V, OS = 3.0V, VIN (a.c. coupled) = FSR = 1.0 VP-P, CL = 15 pF, fCLK = 20 MHz, 50% Duty Cycle, RS = 50Ω, trc = tfc < 4 ns, NOT offset corrected. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C (1). Typical Units Symbol Parameter Conditions Limits (3) (2) (Limits) PD = LOW, STBY = LOW, dc input 1.3 1.4 mA (max) Digital Output Driver Supply Current IDR PD = LOW, STBY = HIGH 0.1 mA (4) PD = HIGH, STBY = LOW or HIGH 0.1 mA PD = LOW, STBY = LOW, dc input 150 169 mW (max) PD = LOW, STBY = LOW, 1 MHz Input 178 mW PWR Power Consumption PD = LOW, STBY = HIGH 27 mW PD = HIGH, STBY = LOW or HIGH <1 mW Change in Full Scale with 2.7V to 3.6V Supply PSRR1 Power Supply Rejection Ratio 90 dB Change Rejection at output with 20 MHz, 250 mVP-P PSRR2 Power Supply Rejection Ratio 52 dB Riding on VA and VD (4) IDR is the current consumed by the switching of the output drivers and is primarily determined by the load capacitance on the output pins, the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR = VDR (CO x fO + C1 x f1 + ... + C9 x f9) where VDR is the output driver power supply voltage, Cn is the total capacitance on the output pin, and fn is the average frequency at which that pin is toggling. AC Electrical Characteristics OS = Low (Multiplexed Mode) The following specifications apply for VA = VD = VDR = +3.0VDC, VREF = 1.0 VDC, GAIN = OF = 0V, OS = 0V, VIN (a.c. coupled) = FSR = 1.0 VP-P, CL = 15 pF, fCLK = 20 MHz, 50% Duty Cycle, RS = 50Ω, trc = tfc < 4 ns, NOT offset corrected. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C (1) Units Symbol Parameter Conditions Typical (2) Limits (3) (Limits) fCLK1 Maximum Clock Frequency 30 20 MHz (min) fCLK2 Minimum Clock Frequency 1 MHz 30 % (min) Duty Cycle 50 70 % (max) Pipeline Delay (Latency) I Data 2.5 Clock Cycles Q Data 3.0 Clock Cycles tr, tf Output Rise and Fall Times 4 ns tOC Offset Correction Pulse Width 10 ns (min) Output Delay from CLK Edge to Data tOD 13 18 ns (max) Valid tDIQ I/Q Output Delay 13 ns tSKEW I/Q to Data Delay ±200 ps tAD Sampling (Aperture) Delay 2.4 ns tAJ Aperture Jitter <10 ps (rms) tVALID Data Valid Time 21 ns Overrange Recovery Time Differential VIN step from 1.5V to 0V 50 ns PD Low to 1/2 LSB Accurate Conversion tWUPD <1 ms (Wake-Up Time) STBY Low to 1/2 LSB Accurate tWUSB 800 ns Conversion (Wake-Up Time) (1) The inputs are protected as shown below. Input voltage magnitude up to 300 mV beyond the supply rails will not damage this device. However, errors in the A/D conversion can occur if the input goes beyond the limits given in these tables. See Figure 2 (2) Typical figures are at TJ = 25°C, and represent most likely parametric norms. (3) Test limits are specified to TI's AOQL (Average Outgoing Quality Level). Performance is ensured only at VREF = 1.0V and a clock duty cycle of 50%. The limits for VREF and clock duty cycle specify the range over which reasonable performance is expected. Tests are performed and limits specified with clock low and high levels of 0.3V and VD − 0.3V, respectively. 8 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: ADC10D020 |
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