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other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.

FEATURES 

HIGH  GAIN  

250MHz TYP. @ 1mA 

ABSOLUTE MAXIMUM RATINGS 

@ 25°C (unless otherwise noted) 

Maximum Temperatures 

Storage Temperature ‐65°C to +200°C 

Operating Junction Temperature ‐55°C to +150°C 

Maximum Power Dissipation 

Continuous Power Dissipation (One side) 

250mW 

Continuous Power Dissipation (Both sides) 

500mW 

Linear Derating factor (One side) 

2.3mW/°C 

Linear Derating factor (Both sides) 

4.3mW/°C 

Maximum Currents 

Collector Current 

10mA 

  

MATCHING CHARACTERISTICS @ 25°C (unless otherwise stated) 

SYMBOL 

CHARACTERISTIC 

MIN 

TYP 

MAX 

UNITS 

CONDITIONS 

Base Emitter Voltage Differential 

‐‐ 

0.2 

0.5 

mV 

 

Base Emitter Voltage Differential 

Change with Temperature 

‐‐ 

0.5 

2 

µV/°C 

TA = ‐55°C to +125°C 

Base Current Differential 

‐‐ 

‐‐ 

5 

nA 

Base Current Differential 

 Change with Temperature 

‐‐ 

‐‐ 

0.3 

nA/°C 

TA = ‐55°C to +125°C 

DC Current Gain Differential 

‐‐ 

5 

‐‐ 

% 

 

ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)

SYMBOL 

CHARACTERISTICS 

MIN. 

TYP. 

MAX. 

UNITS 

CONDITIONS 

Collector to Base Voltage 

60 

‐‐ 

‐‐ 

V 

Collector to Emitter Voltage 

60 

‐‐ 

‐‐ 

V 

Emitter‐Base Breakdown Voltage 

6.2 

‐‐ 

‐‐ 

V 

Collector to Collector Voltage 

100 

‐‐ 

‐‐ 

V 

 

 

DC Current Gain 

200 

‐‐ 

‐‐ 

 

200 

‐‐ 

‐‐ 

 

200 

‐‐ 

‐‐ 

 

Collector Saturation Voltage 

‐‐ 

‐‐ 

0.25 

V 

Emitter Cutoff Current 

‐‐ 

‐‐ 

0.2 

nA 

Collector Cutoff Current 

‐‐ 

‐‐ 

0.2 

nA 

Output Capacitance 

‐‐ 

‐‐ 

2 

pF 

Collector to Collector Capacitance 

‐‐ 

‐‐ 

2 

pF 

Collector to Collector Leakage Current 

‐‐ 

‐‐ 

0.5 

nA 

Current Gain Bandwidth Product 

200 

‐‐ 

‐‐ 

MHz 

NF 

Narrow Band Noise Figure 

‐‐ 

‐‐ 

3 

dB 

f = 1KHz 

Notes: 

1. Absolute Maximum ratings are limiting values above which serviceability may be impaired

2. The reverse base‐to‐emitter voltage must never exceed 6.2 volts; the reverse base‐to‐emitter current must never exceed 10µA. 

 

 

 

 

LS312

MONOLITHIC DUAL

NPN TRANSISTOR

LS312 Features:

Very high gain

Tight matching

Low Output Capacitance

The LS312 is a monolithic pair of NPN transistors

mounted in a single P-DIP package. The monolithic

dual chip design reduces parasitics and gives better

performance while ensuring extremely tight matching.

The 8 Pin P-DIP provides ease of manufacturing, and

the symmetrical pinout prevents improper orientation.

(See Packaging Information).

Linear Systems High Voltage Super-Beta Monolithic Dual NPN

Available Packages:

LS312 in P-DIP

LS312 available as bare die

Please contact Micross for full package and die dimensions:

P-DIP (Top View)