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STP16DPPS05 データシート(PDF) 11 Page - STMicroelectronics |
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STP16DPPS05 データシート(HTML) 11 Page - STMicroelectronics |
11 / 35 page DocID15817 Rev 3 11/35 STP16DPPS05 Timing diagrams 35 5 Timing diagrams Note: OUTn = ON when Dn = H OUTn = OFF when Dn = L Figure 7. Timing diagram Note: 1 Latch and output enable terminals are level-sensitive and are not synchronized with rising or falling edge of LE/DM1 signal. 2 When LE/DM1 terminal is low level, the latch circuit holds previous set of data. 3 When LE/DM1 terminal is high level, the latch circuit refreshes new set of data from SDI chain. 4 When OE/DM2 terminal is at low level, the output terminals Out 0 to Out 15 respond to data in the latch circuits, either ‘1’ for ON or ‘0’ for OFF. 5 When OE/DM2 terminal is at high level, all output terminals are switched OFF. Table 9. Truth table CLOCK LE/DM1 OE/DM2 SERIAL-IN OUT0 ............. OUT7 ................ OUT15 SDO H L Dn Dn ..... Dn - 7 ..... Dn -15 Dn - 15 L L Dn + 1 No change Dn - 14 H L Dn + 2 Dn + 2 ..... Dn - 5 ..... Dn -13 Dn - 13 X L Dn + 3 Dn + 2 ..... Dn - 5 ..... Dn -13 Dn - 13 X H Dn + 3 OFF Dn - 13 |
同様の部品番号 - STP16DPPS05 |
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同様の説明 - STP16DPPS05 |
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