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STA120DJ13TR データシート(PDF) 9 Page - STMicroelectronics |
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STA120DJ13TR データシート(HTML) 9 Page - STMicroelectronics |
9 / 15 page 9/15 STA120 Figure 4. Special Audio Port Formats 12 and 13 Error And Frequency Reporting When SEL is low, error and received frequency information are selected. The error information is encoded on pins E2, E1, and E0, and is decoded as shown in Table 3. When an error occurs, the corresponding error code is latched. Clearing is then accomplished by bringing SEL high for more than eight MCK cycles. The errors have a priority associated with their error code, with validity having the lowest priority that occurred since the last clearing will be selected. Table 3. Error Decoding Figure 5. CBL Timing E2 E1 E0 Error 0 0 0 No Error 0 0 1 Validity Bit High 0 1 0 Confidence flag 0 1 1 Slipped Sample 1 0 0 CRC Error (PRO only) 1 0 1 Parity Error 1 1 0 Bi-Phase Coding Error 1 1 1 No Lock AUX LSB LEFT RIGHT MSB V U C P AUX LSB MSB V U C P LSB LEFT RIGHT MSB LSB MSB AUX VU CP AUX VU CP FSYNC(out) SCK(out) SDATA(out) FSYNC(out) SCK(out) SDATA(out) D98AU987 RIGHT 0 RIGHT 191 LEFT 0 RIGHT 31 RIGHT 191 CBL C0 D98AU988 LEFT 0 LEFT 1 LEFT 32 SDATA Ca-Ce FSYNC ERF, VERF C, U |
同様の部品番号 - STA120DJ13TR |
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同様の説明 - STA120DJ13TR |
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