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HCPL2300 データシート(PDF) 7 Page - Agilent(Hewlett-Packard) |
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HCPL2300 データシート(HTML) 7 Page - Agilent(Hewlett-Packard) |
7 / 12 page 1-294 Notes: 1. Bypassing the power supply line is required with a 0.1 µF ceramic disc capacitor adjacent to each optocoupler as illustrated in Figure 19. The power supply bus for the optocoupler(s) should be separate from the bus for any active loads, otherwise a larger value of bypass capacitor (up to 0.5 µF) may be needed to suppress regenerative feedback via the power supply. 2. Peaking circuits may produce transient input currents up to 100 mA, 500 ns maximum pulse width, provided average current does not exceed 5 mA. Package Characteristics For -40 °C ≤ T A ≤ 85°C, unless otherwise specified. All typicals at TA = 25°C. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Notes Input-Output Momentary VISO 2500 V rms RH ≤ 50%, t = 1 min, 3, 9 Withstand Voltage* TA = 25°C Resistance, Input-Output RI-O 1012 Ω VI-O = 500 V 3 Capacitance, Input-Output CI-O 0.6 pF f = 1 MHz 3 *The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable), your equipment level safety specification, or HP Application Note 1074, “Optocoupler Input-Output Endurance Voltage.” 7. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., VOUT < 0.8 V). 8. CP is the peaking capacitance. Refer to test circuit in Figure 8. 9. In accordance with UL 1577, each optocoupler is momentary withstand proof tested by applying an insulation test voltage ≥ 3000 Vrms for 1 second (leakage detection current limit, II-O ≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b) shown in the VDE 0884 Insulation Character- istics Table, if applicable. 3. Device considered a two terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together. 4. The tPLH propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.5 V point on the trailing edge of the output pulse. 5. The tPHL propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.5 V point on the leading edge of the output pulse. 6. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state (i.e., VOUT > 2.0 V). Figure 3. Typical Output Voltage vs. Forward Input Current vs. Temperature. Figure 2. Typical Input Diode Forward Characteristics. Figure 4. Typical Logic High Output Current vs. Temperature. |
同様の部品番号 - HCPL2300 |
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同様の説明 - HCPL2300 |
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