ATMEGA128A datasheet(51/369 Pages) ATMEL

部品番号	ATMEGA128A

部品情報	8-bit Microcontroller with 128Kbytes

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ATmega 128A [DATASHEET]

Atmel-8151I-8-bit-AVR-ATmega128A_Datasheet-08/2014

10.

System Control and Reset

10.1

Resetting the AVR

During Reset, all I/O registers are set to their initial values, and the program starts execution from the Reset

Vector. The instruction placed at the Reset Vector must be a JMP – absolute jump – instruction to the reset

handling routine. If the program never enables an interrupt source, the interrupt vectors are not used, and

regular program code can be placed at these locations. This is also the case if the Reset Vector is in the

Application section while the interrupt vectors are in the Boot section or vice versa. The circuit diagram in Figure

10-1 shows the reset logic. The the electrical parameters of the reset circuitry are defined in “System and Reset

Characteristics” on page 306.

The I/O ports of the Atmel®AVR® are immediately reset to their initial state when a reset source goes active. This

does not require any clock source to be running.

After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows

the power to reach a stable level before normal operation starts. The time-out period of the delay counter is

defined by the user through the CKSEL fuses. The different selections for the delay period are presented in

“Clock Sources” on page 40.

10.2

Reset Sources

The ATmega128A has five sources of reset:

Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold

(VPOT).

External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the

minimum pulse length.

Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is

enabled.

Brown-out Reset. The MCU is reset when the supply voltage VCC is below the Brown-out Reset threshold

(VBOT) and the Brown-out Detector is enabled.

JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset Register, one of the scan

chains of the JTAG system. Refer to the section “IEEE 1149.1 (JTAG) Boundary-scan” on page 241 for

details.

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