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ILC5061AM-26 データシート(PDF) 3 Page - Impala Linear Corporation |
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ILC5061AM-26 データシート(HTML) 3 Page - Impala Linear Corporation |
3 / 4 page Impala Linear Corporation 3 (408) 574-3939 www.impalalinear.com June 1999 ILC5061 1.7 The following designators 1~6 refer to the timing diagram below. 1. While the input voltage (VIN) is higher than the detect volt- age (VDF), the VOUT output pin is at high impedance state. 2. When the input VIN voltage falls lower than VDF, VOUT drops near to ground voltage 3. If the input voltage further decreases below the mini- mum operating voltage (VMIN), the VOUT output becomes unstable. In this condition, if the VOUT pin is pulled up, VOUT indicates the VIN voltage. 4. During an increase of the input voltage from the VSS voltage, VOUT is not stable in the voltage below the VMIN. Exceeding that level, the output stays at the ground level (VSS) between the minimum operating voltage (VMIN) and the detect release voltage (VDR). 5. If the input voltage increases more than VDR, then the VOUT output pin is at high impedance state. 6. The difference between VDR and VDF is the hysteresis in the system. 6 5 4 3 1 2 INPUT VOLTAGE (V IN) DETECT RELEASE VOLTAGE (V DR) DETECT FAIL VOLTAGE (V DF) MINIMUM OPERATING VOLTAGE (V MIN) GROUND VOLTAGE (V SS) OUTPUT VOLTAGE (V OUT) GROUND VOLTAGE (V SS) SOT-23 Power Supply reset Monitor Functional Description Timing Diagram |
同様の部品番号 - ILC5061AM-26 |
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同様の説明 - ILC5061AM-26 |
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