Data Sheet

AD5426/AD5432/AD5443

Rev. G | Page 5 of 24

TIMING CHARACTERISTICS

Table 2.

Parameter

2.5 V to 5.5 V

4.5 V to 5.5 V

Unit

Test Conditions/Comments

50

50

MHz max

Max clock frequency

20

20

ns min

SCLK cycle time

8

8

ns min

SCLK high time

8

8

ns min

SCLK low time

t41

13

13

ns min

SYNC falling edge to SCLK active edge setup time

5

5

ns min

Data setup time

3

3

ns min

Data hold time

5

5

ns min

SYNC rising edge to SCLK active edge

30

30

ns min

Minimum SYNC high time

t92, 3

80

45

ns typ

SCLK active edge to SDO valid

120

65

ns max

DB15

DB0

SCLK

SYNC

DIN

ALTERNATIVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF

SCLK AS DETERMINED BY CONTROL BITS. TIMING AS PER ABOVE, WITH SCLK INVERTED.

Figure 2. Standalone Mode Timing Diagram

DB15 (N)

DB0 (N)

DB15

(N + 1)

DB0

(N + 1)

SCLK

SDIN

SDO

ALTERNATIVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS

DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING

EDGE OF SCLK. TIMING AS PER ABOVE, WITH SCLK INVERTED.

t6

DB15(N)

DB0(N)

SYNC

Figure 3. Daisy-Chain and Readback Modes Timing Diagram