AD5541_15 データシート(Datasheet) 11 Page - Analog Devices
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Rev. F | Page 11 of 20
THEORY OF OPERATION
The AD5541/AD5542 are single, 16-bit, serial input, voltage
output DACs. They operate from a single supply ranging from
2.7 V to 5.5 V and consume typically 125 µA with a supply of
5 V. Data is written to these devices in a 16-bit word format,
via a 3- or 4-wire serial interface. To ensure a known power-up
state, these parts are designed with a power-on reset function.
In unipolar mode, the output is reset to 0 V; in bipolar mode,
the AD5542 output is set to −V
. Kelvin sense connections for
the reference and analog ground are included on the AD5542.
The DAC architecture consists of two matched DAC sections.
A simplified circuit diagram is shown in Figure 22. The DAC
architecture of the AD5541/AD5542 is segmented. The four
MSBs of the 16-bit data-word are decoded to drive 15 switches,
E1 to E15. Each switch connects one of 15 matched resistors to
either AGND or V
. The remaining 12 bits of the data-word
drive switches S0 to S11 of a 12-bit voltage mode R-2R ladder
2R . . . . .
S1 . . . . .
2R . . . . .
E2 . . . . .
12-BIT R-2R LADDER
FOUR MSBs DECODED
INTO 15 EQUAL SEGMENTS
Figure 22. DAC Architecture
With this type of DAC configuration, the output impedance
is independent of code, while the input impedance seen by
the reference is heavily code dependent. The output voltage is
dependent on the reference voltage, as shown in the following
D is the decimal data-word loaded to the DAC register.
N is the resolution of the DAC.
For a reference of 2.5 V, the equation simplifies to the following:
This gives a V
of 1.25 V with midscale loaded and 2.5 V with
full-scale loaded to the DAC.
The LSB size is V
The AD5541/AD5542 are controlled by a versatile 3- or 4-wire
serial interface that operates at clock rates up to 25 MHz and is
compatible with SPI, QSPI, MICROWIRE, and DSP interface
standards. The timing diagram is shown in Figure 3. Input data
is framed by the chip select input, CS. After a high-to-low
transition on CS, data is shifted synchronously and latched into
the input register on the rising edge of the serial clock, SCLK.
Data is loaded MSB first in 16-bit words. After 16 data bits have
been loaded into the serial input register, a low-to-high transition
on CS transfers the contents of the shift register to the DAC. Data
can be loaded to the part only while CS is low.
The AD5542 has an LDAC function that allows the DAC latch
to be updated asynchronously by bringing LDAC low after CS
goes high. LDAC should be maintained high while data is written
to the shift register. Alternatively, LDAC can be tied perma-
nently low to update the DAC synchronously. With LDAC tied
permanently low, the rising edge of CS loads the data to the DAC.
UNIPOLAR OUTPUT OPERATION
These DACs are capable of driving unbuffered loads of 60 kΩ.
Unbuffered operation results in low supply current, typically
300 μA, and a low offset error. The AD5541 provides a unipolar
output swing ranging from 0 V to V
. The AD5542 can be
configured to output both unipolar and bipolar voltages. Figure 23
shows a typical unipolar output voltage circuit. The code table
for this mode of operation is shown in Table 7.
Figure 23. Unipolar Output
Table 7. Unipolar Code Table
DAC Latch Contents
1111 1111 1111 1111
1000 0000 0000 0000
× (32,768/65,536) = ½ V
0000 0000 0000 0001
0000 0000 0000 0000
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