データシートサーチシステム |
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8XC51GB データシート(PDF) 3 Page - Intel Corporation |
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8XC51GB データシート(HTML) 3 Page - Intel Corporation |
3 / 22 page 8XC51GB PARALLEL IO PORTS The 8XC51GB contains six 8-bit parallel IO ports All six ports are bidirectional and consist of a latch an output driver and an input buffer Many of the port pins have multiplexed IO and control functions Port Pins as Outputs Port 0 has open drain outputs when it is not serving as the external data bus The internal pullup is active only when the pin is outputting a logic 1 during exter- nal memory access An external pullup resistor is required on Port 0 when it is serving as an output port Ports 1 2 3 4 and 5 have quasi-bidirectional out- puts A strong pullup provides a fast rise time when the pin is set to a logic 1 This pullup turns on for two oscillator periods to drive the pin high and then turns off The pin is held high by a weak pullup Writing the P0 P1 P2 P3 P4 or P5 Special Function Register sets the corresponding port pins All six port registers are bit addressable Port Pins as Inputs The pins of all six ports are configured as inputs by writing a logic 1 to them Since Port 0 is an open drain port it provides a very high input impedance Since pins of Port 1 2 3 4 and 5 have weak pullups (which are always on) they source a small current when driven low externally All ports except Port 0 have Schmitt trigger inputs Port States During Reset Ports 0 and 3 reset asynchronously to a one and Ports 1 2 4 and 5 reset to a zero asynchronously PIN DESCRIPTIONS The 8XC51GB will be packaged in the 68-lead PLCC package Its pin assignment is shown in Figure 2 VCC Supply Voltage VSS Circuit Ground Diagram is for Pin Reference Only Package Size is Not to Scale 272337 – 2 OTP only Figure 2 Pin Connections 3 |
同様の部品番号 - 8XC51GB |
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同様の説明 - 8XC51GB |
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