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データシートサーチシステム |
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データシートサーチシステム |
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AD5934 データシート(PDF) 6 Page - Analog Devices |
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AD5934 データシート(HTML) 6 Page - Analog Devices |
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6 / 32 page  AD5934 Data Sheet Rev. C | Page 6 of 32 I2C SERIAL INTERFACE TIMING CHARACTERISTICS VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted (see Figure 2). Table 2. Parameter1 Limit at T MIN, TMAX Unit Description f SCL 400 kHz max SCL clock frequency t 1 2.5 µs min SCL cycle time t 2 0.6 µs min t HIGH, SCL high time t 3 1.3 µs min t LOW, SCL low time t 4 0.6 µs min t HD, STA, start/repeated start condition hold time t 5 100 ns min t SU, DAT, data setup time t 6 2 0.9 µs max t HD, DAT, data hold time 0 µs min t HD, DAT, data hold time t 7 0.6 µs min t SU, STA, setup time for repeated start t 8 0.6 µs min t SU, STO, stop condition setup time t 9 1.3 µs min t BUF, bus free time between a stop and a start condition t 10 300 ns max t R, rise time of SDA when transmitting 0 ns min t R, rise time of SCL and SDA when receiving (CMOS compatible) t 11 300 ns max t F, fall time of SCL and SDA when transmitting 0 ns min t F, fall time of SDA when receiving (CMOS compatible) 250 ns max t F, fall time of SDA when receiving 20 + 0.1 C b 3 ns min t F, fall time of SCL and SDA when transmitting C b 400 pF max Capacitive load for each bus line 1 Guaranteed by design and characterization, not production tested. 2 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to V IH MIN of the SCL signal) to bridge the undefined falling edge of SCL. 3 C b is the total capacitance of one bus line in pF. Note that tR and tF are measured between 0.3 VDD and 0.7 VDD. SCL SDA START CONDITION REPEATED START CONDITION STOP CONDITION t9 t3 t10 t11 t4 t4 t6 t2 t5 t7 t8 t1 Figure 2. I2C Interface Timing Diagram |
同様の部品番号 - AD5934_15 |
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同様の説明 - AD5934_15 |
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