TL16C752B-EP

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SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

A0

28

I

Address 0 select bit. Internal registers address selection.

A1

27

I

Address 1 select bit. Internal registers address selection.

A2

26

I

Address 2 select bit. Internal registers address selection.

Carrier detect (active low). These inputs are associated with individual UART channels A and B. A low

CDA,

40,

I

on these pins indicates that a carrier has been detected by the modem for that channel. The state of

CDB

16

these inputs is reflected in the modem status register (MSR).

Chip select A and B (active low). These pins enable data transfers between the user CPU and the

CSA,

10,

I

TL16C752B for the channel(s) addressed. Individual UART sections (A, B) are addressed by providing

CSB

11

a low on the respective CSA and CSB pins.

Clear to send (active low). These inputs are associated with individual UART channels A and B. A

logic low on the CTS pins indicates the modem or data set is ready to accept transmit data from the

CTSA,

38,

I

TL16C752B. Status can be tested by reading MSR bit 4. These pins only affect the transmit and

CTSB

23

receive operations when auto CTS function is enabled through the enhanced feature register (EFR) bit

7, for hardware flow control operation.

Data bus (bidirectional). These pins are the eight bit, 3-state data bus for transferring information to or

D0–D4

44–48,

I/O

from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive

D5–D7

1–3

serial data stream.

Data set ready (active low). These inputs are associated with individual UART channels A and B. A

DSRA,

39,

I

logic low on these pins indicates the modem or data set is powered on and is ready for data exchange

DSRB

20

with the UART. The state of these inputs is reflected in the modem status register (MSR).

Data terminal ready (active low). These outputs are associated with individual UART channels A and

DTRA,

34,

B. A logic low on these pins indicates that the TL16C752B is powered on and ready. These pins can

O

DTRB

35

be controlled through the modem control register. Writing a 1 to MCR bit 0 sets the DTR output to low,

enabling the modem. The output of these pins is high after writing a 0 to MCR bit 0, or after a reset.

GND

17

Pwr

Signal and power ground

Interrupt A and B (active high). These pins provide individual channel interrupts, INT A and B. INT A

and B are enabled when MCR bit 3 is set to a logic 1, interrupt sources are enabled in the interrupt

INTA,

30,

O

enable register (IER). Interrupt conditions include: receiver errors, available receiver buffer data,

INTB

29

available transmit buffer space or when a modem status flag is detected. INTA-B are in the high-

impedance state after reset.

Read input (active low strobe). A high-to-low transition on IOR loads the contents of an internal register

IOR

19

I

defined by address bits A0–A2 onto the TL16C752B data bus (D0–D7) for access by an external CPU.

Write input (active low strobe). A low-to-high transition on IOW transfers the contents of the data bus

IOW

15

I

(D0–D7) from the external CPU to an internal register that is defined by address bits A0–A2 and CSA

and CSB.

User-defined outputs. This function is associated with individual channels A and B. The state of these

pins is defined by the user through the software settings of the MCR register, bit 3. INTA-B are set to

OPA,

32,

O

active mode and OP to a logic 0 when the MCR-3 is set to a logic 1. INTA-B are set to the 3-state

OPB

9

mode and OP to a logic 1 when MCR-3 is set to a logic 0. See bit 3, modem control register (MCR bit

3). The output of these two pins is high after reset.

Reset. RESET resets the internal registers and all the outputs. The UART transmitter output and the

RESET

36

I

receiver input is disabled during reset time. See TL16C752B external reset conditions for initialization

details. RESET is an active-high input.

Ring indicator (active low). These inputs are associated with individual UART channels A and B. A

RIA,

41,

logic low on these pins indicates the modem has received a ringing signal from the telephone line. A

I

RIB

21

low-to-high transition on these input pins generates a modem status interrupt, if enabled. The state of

these inputs is reflected in the modem status register (MSR).

Request to send (active low). These outputs are associated with individual UART channels A and B. A

low on the RTS pin indicates the transmitter has data ready and waiting to send. Writing a 1 in the

RTSA,

33,

modem control register (MCR bit 1) sets these pins to low, indicating data is available. After a reset,

O

RTSB

22

these pins are set to high. These pins only affect the transmit and receive operation when auto RTS

function is enabled through the enhanced feature register (EFR) bit 6, for hardware flow control

operation.

Receive data input. These inputs are associated with individual serial channel data to the TL16C752B.

RXA,

5,

I

During the local loopback mode, these RX input pins are disabled and TX data is internally connected

RXB

4

to the UART RX input internally.

RXRDYA,

31,

Receive ready (active low). RXRDY A and B goes low when the trigger level has been reached or a

O

RXRDYB

18

timeout interrupt occurs. They go high when the RX FIFO is empty or there is an error in RX FIFO.

Copyright © 2003–2007, Texas Instruments Incorporated

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